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參數(shù)資料
| 型號(hào)： | SN54LVT8980JT |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | SPECIALTY MICROPROCESSOR CIRCUIT, CDIP24 |
| 封裝： | 0.300 INCH, CERAMIC, DIP-24 |
| 文件頁數(shù)： | 18/36頁 |
| 文件大小： | 509K |
| 代理商： | SN54LVT8980JT |
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SN54LVT8980, SN74LVT8980
EMBEDDED TEST-BUS CONTROLLERS
IEEE STD 1149.1 (JTAG) TAP MASTERS WITH 8-BIT GENERIC HOST INTERFACES
SCBS676D – DECEMBER 1996 – REVISED AUGUST 2002
25
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
TDI buffer
The TDI buffer is the serial-to-4
× 8-bit-parallel FIFO that serially receives data at the TDI pin and makes it
available in 8-bit-parallel format for reading by the host. Scan data is expected to be transferred from the
IEEE Std 1149.1 targets in least-significant-bit-first order and is made available for host read in
least-significant-byte-first order. The last data available for host read during a scan command may be a partial
byte, in which case it is justified to D0.
The TDI-buffer status (empty/not empty) is maintained in the status register (bit 7, TDIS). When the TDI-buffer
status is empty, reads to the TDI buffer is held off by RDY inactive and, if the read cycle is aborted prior to RDY
active, the read data is invalid.
The TDI buffer is able to automatically accommodate retiming (pipeline) delays to the target. While operating
a scan command, TDI sampling is delayed by a number of TCK cycles, equal to a value given in the
configurationB register (bits 3–0, RDLY), following the generation of Shift-DR or Shift-IR state, as appropriate.
For the convenience and efficiency of operating scans to the target for which incoming data is not required, the
eTBC supports a special class of output-only scan commands that neither require nor operate the TDI buffer.
While the output-only scan commands are operating, the data received at TDI is ignored and the host need not
perform any read access to the TDI buffer.
While the eTBC is in discrete-control mode, the TDI buffer is not used; instead, the state of the TDO pin is
observed in the discrete-control register. Thus, TMS/TDO sequences that cannot be automatically generated
can still be applied through the eTBC to targets that require such (e.g., near-compliant devices).
For eTBC verification/debugging, the input to the TDI buffer can be selected for loopback from either TDO buffer
or TAP-state (TMS) generator. When either of these loopback modes is selected, although a host-requested
command executes in the eTBC, the target is not affected, as both TMS and TDI are fixed at a high level.
Upon eTBC reset (power up, hardware initiated, or software initiated), the TDI buffer is cleared and assumes
its empty state.
discrete control
The discrete-control block provides the multiplexing and control logic required to support the eTBC’s
discrete-control mode in addition to its automatic modes. While the eTBC is in discrete-control mode, the TAP
signals are fully controllable/accessible to the host via reads/writes to the discrete-control register. No
commands can be initiated/operated while the eTBC is in the discrete-control mode.
Upon eTBC reset (power up, hardware initiated, or software initiated), the discrete-control mode is inactive.
reset
The eTBC provides three mechanisms for comprehensive and equivalent reset – power-up reset,
hardware-initiated reset (RST), and software-initiated reset (SWRST, bit 7 of command register) to the
following effect:
D All eTBC registers are reset to default values as given in Table 1.
D The command/control logic is fully reset.
D The counter is cleared/unloaded. The TDO buffer and TDI buffer are cleared/emptied.
D The TAP-state generator is reset to the Test-Logic-Reset TAP state.
D TDO, TMS, and TRST output high levels; TCK outputs CLKIN/16.
As a consequence, the IEEE Std 1149.1 targets can be expected to be driven synchronously to the
Test-Logic-Reset state no later than the fifth rising edge of TCK (72 CLKIN cycles).
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