參數(shù)資料
型號： SN54LVT8980JT
廠商： TEXAS INSTRUMENTS INC
元件分類： 微控制器/微處理器
英文描述： SPECIALTY MICROPROCESSOR CIRCUIT, CDIP24
封裝： 0.300 INCH, CERAMIC, DIP-24
文件頁數(shù)： 26/36頁
文件大?。?/td> 509K
代理商： SN54LVT8980JT
SN54LVT8980, SN74LVT8980
EMBEDDED TEST-BUS CONTROLLERS
IEEE STD 1149.1 (JTAG) TAP MASTERS WITH 8-BIT GENERIC HOST INTERFACES
SCBS676D – DECEMBER 1996 – REVISED AUGUST 2002
32
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
silicon errata
The descriptions and specifications included in this data sheet represent the intended performance of the
’LVT8990 device. In most cases, these descriptions and specifications also represent the actual performance
of silicon of a given revision. Specific exceptions are noted here. In all cases listed here, subsequent release
of the ’LVT8980 “A” correctly specifies or fixes these problems.
item 1 – operation of host interface (STRB) asynchronous to CLKIN
The host interface, which is timed by STRB, is intended to be, and properly should be, fully asynchronous
relative to CLKIN. In short, the device should function as described in this data sheet, regardless of the timing
relationship between applied STRB and CLKIN.
The ’LVT8990 “X” die, however, fails to function properly when STRB is not synchronous to CLKIN. Specifically,
STRB must be applied, considering adequate setup time requirements, as follows:
SN74LVT8980
VCC = 3.3
± 0.3 V
VCC = 2.7 V
UNIT
MIN
MAX
MIN
MAX
tsu
STRB high before CLKIN
↑
25
ns
Subsequent release of the ’LVT8980 “A” corrects the host interface synchronous problem described here.
workaround
For an ’LVT8980 “X” die design, always operate the host interface (specifically, STRB) synchronously to CLKIN,
maintaining setup time requirements as given above. In most applications, this means that the eTBC CLKIN
is driven from the same original clock source as the host CPU.
item 2 – read of TDI buffer while it is empty (not ready)
When a read is made to the TDI buffer while it is empty (not ready), the RDY pin signal is specified to go low,
indicating that the eTBC presently is not ready to service the requested access. If, while STRB is held low,
subsequent processing of a scan command fills a byte in the TDI buffer, the RDY pin signal is specified to return
high, indicating that the eTBC is ready to complete the access. Correspondingly, the available byte of data from
TDI buffer should be latched onto the data bus such that the host can access this data.
The ’LVT8990 “X” die, however, does not function properly with respect to the actual data latched to the data
bus. That is, if a read is made to TDI buffer while it is empty (not ready), the RDY pin signal will go low as
specified; as well, if the STRB pin signal is held low, and further processing of a scan command fills a byte in
the TDI buffer, the RDY pin signal will return high as specified. However, at the same time that RDY returns high,
the TDI data byte should be latched onto the data bus. If this does not occur, the data that does appear on the
data bus is not valid.
Subsequent release of the ’LVT8980 “A” corrects the read of the TDI buffer, while empty, as described here.
workaround
For an LVT8990 “X” design, always poll the TDI buffer (read status register, bit 7, TDIS) to ensure that it is ready
prior to a desired read to TDI buffer. Of course, such a software-polled mode versus the hardware-inserted
wait-states (RDY) mode (as originally specified, and as proposed to be fixed in ’LVT8980 “A” device revision)
will place more overhead on the CPU and likely reduce throughput as well.
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