- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄98088 > SN54LVT8980JT (TEXAS INSTRUMENTS INC) SPECIALTY MICROPROCESSOR CIRCUIT, CDIP24 PDF資料下載
參數(shù)資料
| 型號： | SN54LVT8980JT |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | SPECIALTY MICROPROCESSOR CIRCUIT, CDIP24 |
| 封裝： | 0.300 INCH, CERAMIC, DIP-24 |
| 文件頁數(shù)： | 31/36頁 |
| 文件大?。?/td> | 509K |
| 代理商： | SN54LVT8980JT |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁當(dāng)前第31頁第32頁第33頁第34頁第35頁第36頁
SN54LVT8980, SN74LVT8980
EMBEDDED TEST-BUS CONTROLLERS
IEEE STD 1149.1 (JTAG) TAP MASTERS WITH 8-BIT GENERIC HOST INTERFACES
SCBS676D – DECEMBER 1996 – REVISED AUGUST 2002
4
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
Terminal Functions
TERMINAL
NAME
DESCRIPTION
A2–A0
Address inputs. A2–A0 form the 3-bit address bus that interfaces the eTBC to its microprocessor/microcontroller host. These
inputs directly index the eTBC register to be accessed (read from or written to).
CLKIN
Clock input. CLKIN is the system clock input for the eTBC. Most operations of the eTBC are synchronous to CLKIN. Internally,
the CLKIN signal is divided by a programmable divisor to generate TCK.
D7–D0
Data
inputs/outputs.
D7–D0
form
the
8-bit
bidirectional
data
bus
that
interfaces
the
eTBC
to
its
microprocessor/microcontroller host. Data in the eTBC registers is accessed (read or written) using this data bus. D7 is
considered the most-significant bit, while D0 is considered the least-significant bit.
GND
Ground
RDY
Ready output. RDY is used to indicate to the microprocessor/microcontroller host whether or not the eTBC is ready to service
the access (read or write) operation that currently is being requested. If RDY remains high following the initiation of an access
cycle (STRB negative edge), then the eTBC is ready. Otherwise, if RDY goes low following the initiation of an access cycle
(STRB negative edge), then the eTBC is not ready. In cases where the eTBC is not ready, subsequent processing in the eTBC
may clear the not-ready state, which allows RDY to return high before the end of the access cycle. In any event, the RDY
output returns high upon the termination of any access cycle (STRB positive edge).
RST
Reset input. RST is used to initiate asynchronous reset of the eTBC. Assertion (low) of RST places the eTBC in a reset state
from which it does not exit until RST is released (high). While RST is low, the eTBC ignores host writes, the RDY, TDO, TMS,
and TRST outputs are high, while TCK outputs CLKIN/16. An internal pullup forces RST to a high level if it has no external
connection.
R/W
Read/write select. R/W is used by the microprocessor/microcontroller host to instruct the eTBC as to whether it is to perform
read access (R/W high) or write access (R/W low). While R/W is high and STRB is low, the D7-D0 outputs are enabled to
drive low and/or high logic levels onto the host data bus. Otherwise, while R/W is low, the D7–D0 outputs are disabled to a
high-impedance state so that the host data bus can drive to the eTBC.
STRB
Read/write strobe. STRB is used by the microprocessor/microcontroller host to instruct the eTBC to initiate (STRB negative
edge) or terminate/conclude (STRB positive edge) an access (read or write) operation. An internal pullup forces STRB to a
high level if it has no external connection.
TCK
Test clock. TCK transmits the TCK signal required by the eTBC’s IEEE Std 1149.1 target(s). All operations of the TAP are
synchronous to TCK. Generally, the TCK signal is generated internally by the eTBC by division of CLKIN by a programmable
divisor. Alternatively, when the eTBC is in its discrete-control mode, a rising edge of TCK is generated on a read to the
discrete-control register, while a falling edge is generated on a write to the discrete-control register.
TDI
Test data input. TDI receives the TDI signal output by the eTBC’s IEEE Std 1149.1 target(s). It is the serial input for shifting
test data from the target(s); it is sampled on the rising edge of TCK and is expected to be transferred from the target(s) on
the falling edge of TCK. An internal pullup forces TDI to a high level if it has no external connection.
TDO
Test data output. TDO transmits the TDO signal required by the eTBC’s IEEE Std 1149.1 target(s). It is the serial output for
shifting test data to the target(s); it is transferred on the falling edge of TCK and is sampled in the target on the rising edge
of TCK.
TMS
Test mode select. TMS transmits the TMS signal required by the eTBC’s IEEE Std 1149.1 target(s). It is the one control signal
that directs the next TAP-controller state of the target(s). It is transferred from the eTBC on the falling edge of TCK and is
sampled in the target(s) on the rising edge of TCK.
TOE
Test-output enable. TOE is the active-low output enable for the eTBC TAP outputs (TCK, TDO, TMS, TRST). When TOE is
inactive (high) the TAP outputs are disabled to a high-impedance state. Otherwise, when TOE is active (low), the TAP outputs
are enabled to drive low and/or high logic levels according to other eTBC functions. An internal pullup forces TOE to a high
level if it has no external connection.
TRST
Test reset. TRST transmits the TRST signal that may be required by some of the eTBC’s IEEE Std 1149.1 target(s). A low
signal at TRST is intended to initiate asynchronous test reset of the connected target(s). Such a low signal at TRST is
generated only when the microprocessor/microcontroller host writes an appropriate value into the eTBC command register
or, while the eTBC is in discrete-control mode, into the discrete-control register.
VCC
Supply voltage
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| SN54LVT8996JT | SPECIALTY MICROPROCESSOR CIRCUIT, CDIP24 |
| SN54LVTH16952WD | LVT SERIES, DUAL 8-BIT REGISTERED TRANSCEIVER, TRUE OUTPUT, CDFP56 |
| SN54LVTH182502AHV | LVT SERIES, DUAL 9-BIT BOUNDARY SCAN REG TRANSCEIVER, TRUE OUTPUT, CQFP68 |
| SN54LVTH18502AHV | LVT SERIES, DUAL 9-BIT BOUNDARY SCAN REG TRANSCEIVER, TRUE OUTPUT, CQFP68 |
| SN54LVTH182512HKC | LVT SERIES, DUAL 9-BIT BOUNDARY SCAN REG TRANSCEIVER, TRUE OUTPUT, CDFP64 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| SN54S00J | 制造商:Texas Instruments 功能描述:NAND Gate 4-Element 2-IN Bipolar 14-Pin CDIP Tube 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| SN54S00W | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| SN54S02J | 制造商:Texas Instruments 功能描述: |
| SN54S03J | 制造商:Rochester Electronics LLC 功能描述:- Bulk 制造商:Texas Instruments 功能描述:2-INPUT NAND GATE (OC) - Rail/Tube |
| SN54S04J | 制造商:Texas Instruments 功能描述:Inverter 6-Element Bipolar 14-Pin CDIP Tube 制造商:Rochester Electronics LLC 功能描述:- Bulk 制造商:Texas Instruments 功能描述:INVERTER 6-ELEM BIPOLAR 14CDIP - Rail/Tube 制造商:Texas Instruments 功能描述:HEX INVERTER *NIC* |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。