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參數(shù)資料
| 型號(hào)： | SN54LVT8980JT |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | SPECIALTY MICROPROCESSOR CIRCUIT, CDIP24 |
| 封裝： | 0.300 INCH, CERAMIC, DIP-24 |
| 文件頁數(shù)： | 28/36頁 |
| 文件大小： | 509K |
| 代理商： | SN54LVT8980JT |
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SN54LVT8980, SN74LVT8980
EMBEDDED TEST-BUS CONTROLLERS
IEEE STD 1149.1 (JTAG) TAP MASTERS WITH 8-BIT GENERIC HOST INTERFACES
SCBS676D – DECEMBER 1996 – REVISED AUGUST 2002
34
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
item 6 – command register internal reset can cause subsequent command writes to be ignored.
When the command register is empty, the eTBC should allow for subsequent commands to be written and
accepted as long as an internal reset is complete. The internal reset lasts for a small number of TCK cycles,
and the eTBC should block subsequent writes to the command register via the RDY output until the internal reset
is complete.
The ’LVT8980 “X” die, however, does not function properly with respect to blocking subsequent command writes
with the RDY pin. The command register can be empty and a new command can be written prior to internal reset
completion. In this case, a subsequent command write could be ignored.
Subsequent release of ’LVT8980 “A” die corrects the problem as described here. Once the command register
is empty, a new command can be written and will be accepted immediately.
workaround
For an ’LVT8980 “X” design, the user should wait at least one full TCK cycle before writing a subsequent
command to the empty command register. The TCK cycle length will depend on the CLKIN frequency and clock
divisor (CDIV) selected. These values should be known, even if the eTBC is operating in gated-TCK mode.
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