參數(shù)資料
型號(hào)： SN54LVT8980JT
廠商： TEXAS INSTRUMENTS INC
元件分類： 微控制器/微處理器
英文描述： SPECIALTY MICROPROCESSOR CIRCUIT, CDIP24
封裝： 0.300 INCH, CERAMIC, DIP-24
文件頁(yè)數(shù)： 27/36頁(yè)
文件大小： 509K
代理商： SN54LVT8980JT
SN54LVT8980, SN74LVT8980
EMBEDDED TEST-BUS CONTROLLERS
IEEE STD 1149.1 (JTAG) TAP MASTERS WITH 8-BIT GENERIC HOST INTERFACES
SCBS676D – DECEMBER 1996 – REVISED AUGUST 2002
33
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
item 3 – incorrect operation when using retiming (pipeline) delays
When setting bits 3-0 of the ConfigurationB register to any non-zero value, the eTBC intends to delay TDI
sampling by a number of TCK cycles. The feature would be used to accommodate retiming (pipeline) delays
from the target scan chains that are electrically distant from the eTBC. This delay is equal to the value set in
the RDLY bit group and has a maximum value of 15.
The ’LVT8980 “X” die, however, does not function properly with respect to the use of retiming delays in
gated-TCK mode. Specifically, when operating in these modes the eTBC may drop bits. When using retiming
delays and free-running-TCK mode, the eTBC does not know when to jump to PAUSE or properly set the TDI
buffer status in the Status register. In either TCK mode described here, the status register does not properly
indicate when the TDO buffer is full.
Subsequent release of the ’LVT8980 “A” corrects the operation of retiming delays as described here. When
using retiming delays, the ’LVT8980 “A” allows the maximum number of TDO writes minus TDI reads to be four,
compared to five, as proposed in the LVT8980 “X”.
workaround
For an ’LVT8980 “X” design, retiming delays should not be used. Any required retiming must be handled with
additional logic that interfaces to the eTBC.
item 4 – when in discrete mode, reads and writes to any register will cause TCK to toggle
When in discrete mode, the eTBC is specified to poll the TDI input and post values on the TDO, TMS, and TRST
outputs based on contents of the Discrete-Control register. The TCK output is specified to toggle during reads
and writes to the Discrete-Control register. Reads generate TCK rising edge, and writes generate TCK falling
edge.
The ’LVT8980 “X” die, functions correctly when reading and writing to the Discrete-Control register. However,
when in discrete mode and reading or writing to any register, the eTBC generates TCK rising edges and falling
edges, respectively. The intended operation is to toggle TCK only when reading or writing to the
Discrete-Control register.
Subsequent release of the ’LVT8980 “A” corrects the discrete mode problem as described here.
workaround
For an ’LVT8980 “X” design, when in discrete mode, reading or writing to registers other than the discrete control
register should be avoided.
item 5 – output pulse glitch on RDY output
When attempting to write to or read any of the eTBC registers, if any condition exists to prevent that operation,
RDY will be asserted low in response to the low transition on STRB. If RDY remains high when STRB goes low,
it should remain high for the duration of the low state of STRB.
The ’LVT8980 “X” die, however, does not function properly with respect to RDY remaining high throughout the
duration of the low state of STRB. In certain cases, while performing writes to the TDO register, RDY may glitch
low for several nanoseconds, then return high. This glitch always follows a high transition on the internal TCK,
which always follows a high transition on CLKIN.
Subsequent release of ’LVT8980 “A” die corrects the problem as described here. If RDY does not go low,
following a low transition on STRB, then it will stay high for the duration of the low state of STRB.
workaround
For an ’LVT8980 “X” design, the user should not use transitions on RDY to trigger logic events. Also, while STRB
is held low during TDO writes, the user should not rely on the accuracy of the state of RDY until approximately
15 nanoseconds following a high transition of CLKIN.
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