
Rev. 2.0, 09/02, page 8 of 732
Type
Symbol
RES
I/O
Name
Function
Input
Power on
reset
When this pin is driven low, the chip
becomes to power on reset state.
MRES
Input
Manual reset
When this pin is driven low, the chip
becomes to manual reset state.
WDTOVF
*
Output
Watchdog
timer overflow
Output signal for the watchdog timer
overflow.
If this pin needs to be pulled-down, the
resistance value must be 1 M
or higher.
External device can request the release of
the bus mastership by setting this pin low.
BREQ
Input
Bus request
System
control
BACK
Output
Bus
acknowledge
Shows that the bus mastership has been
released for the external device. The
device that had issued the
BREQ
signal
can know that bus mastership has been
released for itself by receiving the
BACK
signal.
NMI
Input
Non-maskable
interrupt
Non-maskable interrupt pin. If this pin is
not used, it should be fixed high.
IRQ7
IRQ3
IRQ6
IRQ2
IRQ5
IRQ1
IRQ4
IRQ0
Input
Interrupt
request 7 to 0
These pins request a maskable interrupt.
One of the level input or edge input can be
selected In case of the edge input, one of
the rising edge, falling edge, or both can
be selected.
Interrupts
IRQOUT
Output
Interrupt
request output
Shows that an interrupt cause has
occurred. The interrupt cause can be
recognized even in the bus release state.
Address bus
A21 to A0
Output
Address bus
Output the address.
Data bus
SH7144:
D15 to D0
SH7145:
D31 to D0
CS3
CS1
CS2
CS0
RD
WRHH
(SH7145
only)
WRHL
(SH7145
only)
Input/
Output
Data bus
SH7144: Bi-directional 16-bit bus
SH7145: Bi-directional 32-bit bus
Output
Chip select
3 to 0
Chip select signal for external memory or
devices.
Output
Read
Shows reading from external devices.
Output
Write HH
Shows writing into the HH 8 bits (bits 31 to
24) of the external data.
Bus control
Output
Write HL
Shows writing into the HL 8 bits (bits 23 to
16) of the external data.