
Rev. 2.0, 09/02, page 457 of 732
Time (at Maximum Transfer Rate) [ns]
Item
t
pcyc
Effect
of t
Sr
/t
Sf
(max)
I
2
C bus
specification
(min)
P
φ
=
10MHz
P
φ
=
16MHz
P
φ
=
20MHz
P
φ
=
25MHz
P
φ
=
33MHz
P
φ
=
40MHz
Standard
mode
250
4000
4650
4688
4700
4710
4720
4725
t
STAHO
0.5 t
SCLO
1 t
pcyc
(
t
Sf
)
High-speed
mode
250
600
900
938
950
960
970
975
Standard
mode
1000
4700
9000
9000
9000
9000
9000
9000
t
STASO
1 t
SCLO
(
t
Sr
)
High-speed
mode
300
600
2200
2200
2200
2200
2200
2200
Standard
mode
1000
4000
4200
4125
4100
4080
4061
4050
t
STOSO
0.5 t
SCLO
+2 t
pcyc
(
t
Sr
)
High-speed
mode
300
600
1150
1075
1050
1030
1011
1000
Standard
mode
1000
250
3400
3513
3550
3580
3609
3625
t
SDASO
As
mast
er
1 t
SCLLO
*
3 t
pcyc
(
t
Sr
)
2
High-speed
mode
300
100
700
813
850
880
909
925
Standard
mode
1000
250
3400
3513
3550
3580
3609
3625
t
SDASO
As
slave
1 t
SCLL
*
3 t
pcyc
*
(
t
Sr
)
2
2
High-speed
mode
300
100
700
813
850
880
909
925
Standard
mode
0
0
300
188
150
120
91
75
t
SDAHO
3 t
pcyc
High-speed
mode
0
0
300
188
150
120
91
75
Notes: 1. Apply one or more of the following measures to satisfy the I
specification.
Ensure that the interval between the setting of the start condition and of the stop
condition is sufficient.
Adjust the rise and fall times by changing the values of the pull-up resistors and load
capacitance.
Adjust the system by decreasing the transfer rate.
Select a slave device with an input timing that permits the I/O timing.
The values in the above table are changed by the setting of the IICX bit and the CKS2
to CKS0 bits. Since the maximum transfer rate may not be achievable, depending on
the frequency, check whether or not the I
the actual conditions that are set.
2. Calculated from the I
ns/min.)
2
C bus interface
2
C bus interface specification is satisfied under
2
C bus specifications (standard 4700 ns/min, high-speed: 1300