
Rev. 2.0, 09/02, page 719 of 732
Item
Page
Revisions (See Manual for Details)
11.9.5 Usage Note
347
Added.
Figure 12.1 Block
Diagram of WDT
350
Note added.
Overflow
Interrupt
control
ITI (interrupt
request signal)
Internal reset
signal
*
2
Reset
control
φ
/2
φ
/64
φ
/128
φ
/256
φ
/512
φ
/1024
φ
/4096
φ
/8192
Clock
Clock
select
Internal clock
Notes: 1.
If this pin needs to be pulled-down,the resistance value must be 1M or higher.
2.
The internal reset signal can be generated by register setting.
Power-on reset or manual reset can be selected.
*
1
Table 13.3 BRR
Settings for Various Bit
Rates (Asynchronous
Mode) (4)
375
Note added.
Table 13.6 BRR
Settings for Various Bit
Rates (Clocked
Synchronous Mode) (1)
to (4)
378,
379
Setting values amended.
Table 13.7 Maximum
Bit Rate with External
Clock Input (Clocked
Synchronous Mode)
380
Note deleted.
Figure 13.7 Sample
Serial Transmission
Flowchart
387
Figure amended.
[1]
Initialization
Start transmission
[1] SCI initialization:
Set the TxD pin using the PFC.
After the TE bit is set to 1, a frame
period of 1s is output, and
transmission is enabled. This action
doesn't initiate immediate data
transmission.
Figure 13.8 Example of
SCI Operation in
Reception
388
Figure amended.
0
D0
D1
D7
0/1
1
0
D0
D1
D7
0/1
1
1
1
Data
Start
bit
Parity
bit
Stop
bit
Start
bit
Data
Parity
bit
Stop
bit
Idle state
(mark state)
RxD
Figure 13.11 Sample
Multiprocessor Serial
Transmission Flowchart
394
Figure amended.
[1]
Initialization
Start transmission
[1]
SCI initialization:
Set the TxD pin using the PFC.
After the TE bit is set to 1, a
frame period of 1s is output, and
transmission is enabled. This
action doesn't initiate immediate
data transmission.