
Rev. 2.0, 09/02, page 1 of 732
Section 1 Overview
The SH7144 Series single-chip RISC (Reduced Instruction Set Computer) microcomputers
integrate a Hitachi-original RISC CPU core with peripheral functions required for system
configuration.
The SH7144 series CPU has a RISC-type instruction set
.
Most instructions can be executed in one
state (one system clock cycle), which greatly improves instruction execution speed
.
In addition,
the 32-bit internal-bus architecture enhances data processing power. With this CPU, it has become
possible to assemble low cost, high performance/high-functioning systems, even for applications
that were previously impossible with microcomputers, such as real-time control, which demands
high speeds.
In addition, the SH7144 series includes on-chip peripheral functions necessary for system
configuration, such as a direct memory access controller (DMAC), large-capacity ROM and
RAM, timers, a serial communication interface (SCI), an A/D converter, an interrupt controller
(INTC), and I/O ports. As an option, an I
2
C bus interface can also be incorporated.
ROM and SRAM can be directly connected to the SH7144 MCU by means of an external memory
access support function. This greatly reduces system cost.
There are two versions of on-chip ROM: F-ZTAT
includes flash memory, and mask ROM. The flash memory can be programmed with a
programmer that supports SH7144 series programming, and can also be programmed and erased
by software. This enables LSI chip to be re-programmed at a user-site while mounted on a board.
TM
*
(Flexible Zero Turn Around Time) that
Note: * F-ZTAT
TM
is a registered trademark of Hitachi, Ltd.
1.1
Features
Central processing unit with an internal 32-bit RISC (Reduced Instruction Set Computer)
architecture
Instruction length: 16-bit fixed length for improved code efficiency
Load-store architecture (basic operations are executed between registers)
Sixteen 32-bit general registers
Five-stage pipeline
On-chip multiplier: multiplication operations (32 bits
×
32 bits
→
64 bits) executed in two
to four cycles
C language-oriented 62 basic instructions
Various peripheral functions
Direct memory access controller (DMAC)
Data transfer controller (DTC)