
Rev. 2.0, 09/02, page 567 of 732
Port E in the SH7145 is an input/output port with the 16 pins shown in figure 18.8.
PE15 (I/O) / TIOC4D (I/O) / DACK1 (output) /
(output)
PE14 (I/O) / TIOC4C (I/O) / DACK0 (output)
PE13 (I/O) / TIOC4B (I/O) /
(input)
PE12 (I/O) / TIOC4A (I/O) / TCK (input)
*
/ TXD3 (output)
PE11 (I/O) / TIOC3D (I/O) / TDO (output)
*
/ RXD3 (input)
PE10 (I/O) / TIOC3C (I/O) / TXD2 (output) / TDI (input)
*
PE9 (I/O) / TIOC3B (I/O) /
(input)
*
/ SCK3 (I/O)
PE8 (I/O) / TIOC3A (I/O) / SCK2 (I/O) / TMS (input)
*
PE7 (I/O) / TIOC2B (I/O) / RXD2 (input)
PE6 (I/O) / TIOC2A (I/O) / SCK3 (I/O) / AUDATA0 (I/O)
*
PE5 (I/O) / TIOC1B (I/O) / TXD3 (output) / AUDATA1 (I/O)
*
PE4 (I/O) / TIOC1A (I/O) / RXD3 (input) / AUDATA2 (I/O)
*
PE3 (I/O) / TIOC0D (I/O) / DRAK1 (output) / AUDATA3 (I/O)
*
PE2 (I/O) / TIOC0C (I/O) /
(input) /
(input)
*
PE1 (I/O) / TIOC0B (I/O) / DRAK0 (output) / AUDMD (input)
*
PE0 (I/O) / TIOC0A (I/O) /
(input) / AUDCK (I/O)
*
Note:
*
Only for the F-ZTAT version (no corresponding function in the mask version).
Port E
Figure 18.8 Port E (SH7145)
18.5.1
Register Descriptions
Port E has the following register. For details on register addresses and register states during each
processing, refer to section 25, List of Registers.
Port E data register L (PEDRL)
18.5.2
Port E Data Register L (PEDRL)
The port E data register L (PEDRL) is a 16-bit readable/writable registers that stores port E data.
Bits PE15DR to PE0DR correspond to pins PE15 to PE0 (multiplexed functions omitted here).
When a pin functions is a general output, if a value is written to PEDRL, that value is output
directly from the pin, and if PEDRL is read, the register value is returned directly regardless of the
pin state.