
2000 Sep 07
34
Philips Semiconductors
Preliminary specification
Universal Timeslot Interchange
SC4000
Local Bus
Local bus Framing Mode [1:0] (C_[7:6])
(Read/Write)
Local Bus SI Sample Position (C_17)
(Read/Write)
Local bus SO Output Delay Enable
(C_19) (Read/Write)
Local bus L_CLK Polarity (C_24)
(Read/Write)
Local bus L_FS Polarity (C_25)
(Read/Write)
Local bus L_FS Position (C_[27:26])
(Read/Write)
Local bus L_CLK & L_FS Rate (C_28)
(Read/Write)
Local bus L_CLK DPLL Enable (C_29)
(Read/Write)
Local bus L_CLK 8.192 MHz 62.5%
Duty Cycle (C_30) (Read/Write)
Message Channel
Message Channel Registered TXD
Enable (C_12) (Read/Write)
Message Channel TXD_0 or TXD_1
Select (C_13) (Read/Write)
Message Channel Clock Duty Cycle
Select (C_14) (Read/Write)
Message Channel Output Disable
(W/ loopback) (C_15) (Read/Write)
Watchdog
Clock Watchdog Enable (C_48)
(Read/Write)
Microprocessor Watchdog Enable
(C_49) (Read/Write)
Interrupt
SCbus CLKFAIL Latch Set Polarity
Select (C_50) (Read/Write)
SCbus CLKFAIL Latch Debounce
Enable (C_51) (Read/Write)
Frame Boundary Latch Set Delay Enable
(C_52) (Read/Write)
INT_0 Mask_N (C_53) (Read/Write)
INT_0 Output Polarity (C_54)
(Read/Write)
INT_0 Output Driver (C_55)
(Read/Write)
SCbus CLKFAIL Latch (C_56)
(Read Only)
Frame Boundary Latch (C_57)
(Read only)
Internal Master PLL Error Latch (C_58)
(Read Only)
SCbus Error Indicator (C_59)
(Read Only)
SCbus CLKFAIL Latch Clear_N (C_60)
(Read/Write)
Frame Boundary Latch Clear_N (C_61)
(Read/Write)
Internal Master PLL Error Latch
Clear_N (C_62) (Read/Write)
SCbus SCLKX2N Error Latch (C_64)
(Read Only)
SCbus SCLKX2NA Error Latch (C_65)
(Read only)
SCbus SCLK Error Latch (C_66)
(Read only)
SCbus SCLKA Error Latch (C_67)
(Read only)
SCbus SCLKX2N Error Latch Clear_N
(C_68) (Read/Write)
SCbus SCLKX2NA Error Latch Clear_N
(C_69) (Read/Write)
SCbus SCLK Error Latch Clear_N
(C_70) (Read/Write)
SCbus SCLKA Error Latch
Clear_N(C_71) (Read/Write
SCbus FSYNCN Error Latch (C_72)
(Read Only)
SCbus FSYNCNA Error Latch (C_73)
(Read Only)
SCbus Clock Master Error Latch (C_74)
(Read Only)
SCbus FSYNCN Error Latch Clear_N
(C_76) (Read/Write)
SCbus FSYNCNA Error Latch Clear_N
(C_77) (Read/Write)
SCbus Clock Master Error Latch
Clear_N (C_78) (Read/Write)
SCbus SREF_8K NE SREF_8KA Error
Latch (C_80)(Read only)
SCbus CLKFAIL NE CLKFAILA Error
Latch (C_81)(Read only)
SCbus MC NE MCA Error Latch
(C_82)(Read only)
SCbus SD Error Indicator (C_83)
(Read only)
SCbus SREF_8K NE SREF_8KA Error
Latch Clear_N (C_84)(Read/Write)
SCbus CLKFAIL NE CLKFAILA Error
Latch Clear_N (C_85)(Read/write)
SCbus MC NE MCA Error Latch
Clear_N (C_86)(Read/Write)
SCbus SD Error Latch Clear_N
(C_87)(Read/Write)
SCbus SD_[15:0] Error Latch
(C_[103:88]) (Read only)
Reserved Bit
No use Bit (C_31) (Read only)
No use Bit (C_63) (Read only)
No use Bit (C_75) (Read only)
No use Bit (C_79) (Read only)
TYPICAL INTERNAL REGISTER ACCESS
Typical Write Internal Register Access
1. Read Command/Status register and
test for NOT BUSY. (Note1)
2. Write Data into Internal Address reg-
ister, Low Byte Data register, and
High Byte Data register as required.
3. Write a “1” to the WRITE Command
bit in the Command/Status register.
(Note 4)
4. Read Command/Status register and
test for NOT BUSY. (Note 2)
Typical Read Internal Register Access
1. Read Command/Status register and
test for NOT BUSY. (Note 1)
2. Write Data into Internal Address
register.
3. Write a “1” to the READ Command
bit in the Command/Status register.
(Note 3 & 4)