參數(shù)資料
型號(hào)： SC4000
廠商： NXP SEMICONDUCTORS
元件分類(lèi)： 路由/交換
英文描述： Pressure Transducer, Series 19 mm, Compensated, Pressure Range: 0 psi to 200 psi, Vacuum Gage, 1/8-27 NPT, 10 Vdc excitation
中文描述： TELECOM, DIGITAL TIME SWITCH, PQFP100
封裝： TQFP-100
文件頁(yè)數(shù)： 30/52頁(yè)
文件大?。?/td> 179K
代理商： SC4000
2000 Sep 07
30
Philips Semiconductors
Preliminary specification
Universal Timeslot Interchange
SC4000
When C_43=1 this field selects the refer-
ence for the External Master PLL which
is output on REF_8K_OUT pin7.
000 ->Free-run (driven high) (Default)
001 ->Free-run (driven high)
010 ->Free-run (driven high)
011 -> SREF_8K
100 -> REF_8K_0
101 -> REF_8K_1
110 -> tri-state (Z)
111 -> tri-state (Z)
Internal/External Master PLL Select (C_43)
(Read/Write)
This bit selects the Master PLL to be
either Internal or External.
0 -> Internal Master PLL (Default)
1 -> External Master PLL
SCbus SREF_8K Source Select [1:0]
(C_[45:44]) (Read/Write)
00 -> REF_8K_0 (Default)
01 -> REF_8K_1
10 -> REF_8K_2
11 -> REF_8K_3
SCbus SREF_8K Output Enable (C_46)
(Read/Write)
0 -> SCbus SREF_8K Disabled (Z)
(Default)
1 -> SCbus SREF_8K Enabled
SCbus SCLK 8.192 MHz 62.5% Duty Cycle
(C_47) (Read/Write)
0 -> SCLK 8.192 MHz 62.5% Duty
Cycle Disabled (Default)
1 -> SCLK 8.192 MHz 62.5% Duty
Cycle Enabled
Note:
The SCbus Framing Mode
(C_[5:4]) must be set to 8.192 Mb/s to
enable SCLK 8.192 MHz 62.5% duty
cycle. If Enable (C_22=0) SCLKX2N
will be driven high.
Configuration Register Byte 6, IAR = 06H
Clock Watchdog Enable (C_48) (Read/Write)
This bit enables the Clock Watchdog.
0 -> Clock Watchdog Disabled (Default)
1 -> Clock Watchdog Enabled
Note
: When enabled, C_48 is read back a
1 until the Master PLL clocks for 125us
(+/- 50%); then it reads back a 0. This
mode is provided to allow detection of a
missing PLL clock. This information can
then be used to take a master off the bus
or to remove a secondary clock master
from the fallback list. The Clock Watch-
dog must be re-armed after each test. To
re-arm, the Clock Watchdog C_48 must
be cleared to “0” and then set to “1”.
Mcroprocessor Watchdog Enable (C_49)
(Read/Write)
This bit enables the Microprocessor
Watchdog.
0 -> Microprocessor Watchdog Dis-
abled (Default)
1 -> Microprocessor Watchdog Enabled
Note:
When enabled the SC4000 will be
put into reset after the Master PLL
clocks for 256 ms (+/-50%).
This mode is provided to force an
SC4000 off the SCbus when it’s control-
ling microprocessor fail to reset the
watchdog. Each time C_49 is cleared
“0” and the set “1” the watchdog count
is reset.
SCbus CLKFAIL Latch Set Polarity Select
(C_50) (Read/Write)
This bit selects the polarity of the SCbus
CLKFAIL signal that will set the
CLKFAIL latch.
0 -> CLKFAIL latch set when
CLKFAIL = 0 (Default)
1 -> CLKFAIL latch set when
CLKFAIL = 1
Note 1:
The CLKFAIL polarity bit can be
used to generate interrupts on both ends
of a CLKFAIL transition. The CLKFAIL
= 0 interrupt is used by the new primary
clock source to determine that the tran-
sition from secondary to primary has
been made. The CLKFAIL = 1 interrupt
is used by a secondary clock source to
determine that the primary clock source
has given up the bus. A third module
(neither primary or secondary) could
use this interrupt to monitor the CLK-
FAIL transition and act as a system
watchdog.
Note 2:
Only change CLKFAIL polarity
when CLKFAIL Latch Clear_N
(C_60) = 0.
SCbus CLKFAIL Latch Debounce Enable (C_51)
(Read/Write)
0 -> CLKFAIL Latch Debounce Disabled
(Default)
1 -> CLKFAIL Latch Debounce Enabled
Note 1
: A clock must be present from the
Master PLL to enable this feature.
Note 2:
The debounce logic requires that
the CLKFAIL signal be sampled with the
same value for two consecutive Master
PLL clocks before it can set the CLK-
FAIL Latch.
LBDR_[7:0]
C_[55:48]
Definition
0
48
Clock Watchdog
Enable
1
49
Mcroprocessor
Watchdog Enable
2
50
SCbus CLKFAIL
Latch Set Polarity
Select
3
51
SCbus CLKFAIL
Latch Debounce
Enable
4
52
Frame Boundary
Latch Set Delay Enable
5
53
INT_0 Mask_n
6
54
INT_0 Polarity
7
55
INT_0 Output Driver
Configuration
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