參數(shù)資料
型號(hào)： SC4000
廠商： NXP SEMICONDUCTORS
元件分類(lèi)： 路由/交換
英文描述： Pressure Transducer, Series 19 mm, Compensated, Pressure Range: 0 psi to 200 psi, Vacuum Gage, 1/8-27 NPT, 10 Vdc excitation
中文描述： TELECOM, DIGITAL TIME SWITCH, PQFP100
封裝： TQFP-100
文件頁(yè)數(shù)： 29/52頁(yè)
文件大?。?/td> 179K
代理商： SC4000
2000 Sep 07
29
Philips Semiconductors
Preliminary specification
Universal Timeslot Interchange
SC4000
SCbus Alternate (A) Signals Output Enable
(C_23) (Read/Write)
This bit enables the SCbus Alternate
(“A”) Signals Output (when required).
When disabled, the outputs are
tri-stated.
0-> SCbus Alternate (“A”) Signals
Output Disabled (Default)
1-> SCbus Alternate (“A”) Signals
Output Enabled
Configuration Register Byte 3, IAR = 03H
Local bus L_CLK Polarity (C_24)
(Read/Write)
0- > L_CLK Non-Inverted (Default)
1- > L_CLK Inverted
Local bus L_FS Polarity (C_25) (Read/Write)
0- > L_FS Non-Inverted (Default)
1- > L_FS Inverted
Local bus L_FS Position (C_[27:26])
(Read/Write)
00 -> L_FS occurs during the last clock
period of the frame (Default)
01 -> L_FS straddles the frame
boundary
10 -> L_FS occurs during the first clock
period of the frame
11 -> Reserved
Local bus L_CLK & L_FS Rate (C_28)
(Read/Write)
0 -> L_CLK & L_FS equal to the Local
bus data rate (Default)
1 -> L_CLK & L_FS equal to 2 times
the Local bus data rate
Note:
To select the 2x rate, SCLKX2N
must be present or the Local bus fram-
ing mode must be set to a data rate that
is either higher or lower than the SCbus
framing mode.
Local bus L_CLK DPLL Enable (C_29)
(Read/Write)
This mode is provided to maintain a
continuous L_CLK for network inter-
faces during a Clock Fail condition.
0->L_CLK DPLL Disabled (Default)
1->L_CLK DPLL Enabled
Note 1
: The Local bus Framing Mode
(C_[7:6]) must be set to 2.048 Mb/s and
a 65.536MHz Clock must be supplied on
X_IN.
Note 2:
When Enabled L_CLK will run
free during an SCbus Clock Fail
condition.
Note 3: When the DPLL enters the free-
run, the Local bus SO lines are tri-stated.
Local bus L_CLK 8.192 MHz 62.5% Duty
Cycle (C_30) (Read/Write)
0 -> L_CLK 8.192 MHz 62.5% Duty
Cycle Disabled (Default)
1 -> L_CLK 8.192 MHz 62.5% Duty
Cycle Enabled
Note
: To enable L_CLK 8.192 MHz
62.5% Duty Cycle, the Local bus Fram-
ing Mode (C_[7:6]) must be set to 8.192
Mb/s and the SCbus Framing Mode
(C_[5:4]) must be set to 4.096 Mb/s or
2.048 Mb/s. C_28 must be set to 0.
Configuration Register Byte 4, IAR = 04H
Version/Revision Status (C_[39:32])
The Version/Revision Register is a read
only register. It is intended for use to
identify SCxxxx devices.
This field may be changed in future
SCxxxx designs. It is recommended that
a test of this field be included in all ver-
sions of firmware interface code.
The initial release of the SC4000 will be
Version/Revision = 10H
Configuration Register 5,IAR = 05H
Master PLL Reference Select [2:0]
(C_[42:40]) (Read/Write)
When C_43=0 this field selects the refer-
ence for the Internal Master PLL.
000 -> Free-run (Default)
001 -> Free-run
010 -> Free-run
011 -> SREF_8K
100 -> REF_8K_0
101 -> REF_8K_1
110 -> REF_8K_2
111 -> REF_8K_3
LBDR_[7:0]
C_[31:24]
Definition
0
24
Local bus L_CLK
Polarity
1
25
Local bus L_FS
Polarity
[3:2]
[27:26]
Local bus L_FS
Position [1:0]
4
28
Local bus L_CLK
and L_FS Rate
5
29
Local bus L_CLK
DPLL Enable
6
30
Local bus L_CLK
8.192 MHz 62.5%
duty cycle Enable
7
31
Reserved (0)
(Read only)
LBDR_[7:0]
C_[39:32]
Definition
[3:0]
[35:32]
Revision field (read
only)
[7:4]
[39:36]
Version field (SC4000
= 1H, SC2000 = 0H)
(Read only)
LBDR_[7:0]
C_[47:40]
Definition
[2:0]
[42:40]
Master PLL Reference
Select [2:0]
3
43
Internal/External
Master PLL Select
[5:4]
[45:44]
SCbus SREF_8K
Source Select [1:0]
6
46
SCbus SREF_8K
Output Enable
7
47
SCbus SCLK 8.192
MHz 62.5% duty
cycle enable
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