參數(shù)資料
型號： SC4000
廠商： NXP SEMICONDUCTORS
元件分類： 路由/交換
英文描述： Pressure Transducer, Series 19 mm, Compensated, Pressure Range: 0 psi to 200 psi, Vacuum Gage, 1/8-27 NPT, 10 Vdc excitation
中文描述： TELECOM, DIGITAL TIME SWITCH, PQFP100
封裝： TQFP-100
文件頁數(shù)： 14/52頁
文件大?。?/td> 179K
代理商： SC4000
2000 Sep 07
14
Philips Semiconductors
Preliminary specification
Universal Timeslot Interchange
SC4000
FUNCTION DESCRIPTION
Switching
The SC4000 allows data switching
through the microprocessor interface in
any of the following three directions:
From any local bus serial channel (SI)
or parallel data bus D_[7:0] input to
any SCbus channel (SD) output
From any SCbus channel (SD) input
to any output of the local bus serial
channel (SO) or parallel data bus
D_[7:0]
From any of local bus serial channel
(SI) or parallel data bus D_[7:0] input
directly through an internal local
connect bus to any local bus serial
channel (SO) output
As shown in Figure 1, each input SI and
output SO channel is mapped to one of
128 unique locations in the destination
routing memory and source routing
memory, respectively. So data stored in
the destination or source routing mem-
ory selects the timeslot and serial port of
the SCbus. All data is buffered through
the input holding register, output hold-
ing register or parallel access register for
a switching matrix with one frame delay.
PLL Timing and Clock Control
The SC4000 provides the option of us-
ing the internal master PLL (C_43 = 0)
or an external master PLL (C_43 = 1).
As shown in Figure 2, the internal
master PLL generates a clock that is fre-
quency-locked to an 8 KHz reference in-
put of either SREF_8K or REF_8K[3:0].
When the SC4000 is enabled as SCbus
master (C_0 =1), a state machine inside
the SC4000 uses this clock to generate
SCLK, SCLKX2N and a “free-running”
FSYNCN signal based on the speed of
the SCbus and the clock frequency. The
internal master PLL runs free when:
Put into free run mode (ignoring
reference input changes) by control
C_[42:40]
The 8 KHz reference input is static
“1” or “0”
The input of X_IN is less than 65.536
MHz.
The internal master PLL can also gener-
ate an interrupt if it cannot lock the
selected 8 KHz reference input.
Figure 2. Internal Master PLL (C_43 = 0) Function Block
EXTERNAL
CRYSTAL or OSC
C_0, C_3, C_[23:22]
SCLKX2N
SCLKX2NA
SCLK
SCLKA
46, 47
49, 50
SREF_8K
SREF_8KA
51, 52
REF_8K_[3:0]
C_[42:40]
C_[45:44]
C_3, C_23, C_46
X
X
1
2
Master PLL
Reference
8 K Select
SCbus
SREF_8K
Source
Select
Clock
Master PLL
SCbus
4, 5, 6, 7
FSYNCN
FSYNCNA
54, 55
65.536 MHz
Programmable
Divider
C_[10:8], C_[5:4]
To Internal Watchdogs and
SCbus Error Detectors
C_2
Primary
or
Alternate
Select
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
SC4002A 制造商:未知廠家 制造商全稱:未知廠家 功能描述:LCD MODULES SC4002A ( 40 CHARACTERS x 2 LINES )
SC4002ALM-6 功能描述:AMPLIFIER TRIP UNIVERSAL INPUT D 制造商:cynergy 3 系列:SC 零件狀態(tài):在售 類型:過程感應(yīng) 跳脫狀態(tài):通電高/低 跳脫范圍:- 延遲時間:無延遲 電壓 - 電源:16 ~ 30VDC 輸出類型:繼電器 電路:SPDT（1 C 形） 不同電壓時的觸頭額定電流:3A @ 240VAC 安裝類型:DIN 軌道 工作溫度:0°C ~ 55°C 標(biāo)準(zhǔn)包裝:1
SC4004 制造商:Ferraz Shawmut 功能描述:
SC4004A 制造商:未知廠家 制造商全稱:未知廠家 功能描述:LCD MODULES 40 CHARACTERS x 4 LINES
SC4004B 制造商:未知廠家 制造商全稱:未知廠家 功能描述:40 CHARACTERS x 4 LINES
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