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參數(shù)資料
| 型號： | SC4000 |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 路由/交換 |
| 英文描述： | Pressure Transducer, Series 19 mm, Compensated, Pressure Range: 0 psi to 200 psi, Vacuum Gage, 1/8-27 NPT, 10 Vdc excitation |
| 中文描述： | TELECOM, DIGITAL TIME SWITCH, PQFP100 |
| 封裝： | TQFP-100 |
| 文件頁數(shù)： | 31/52頁 |
| 文件大小： | 179K |
| 代理商： | SC4000 |
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2000 Sep 07
31
Philips Semiconductors
Preliminary specification
Universal Timeslot Interchange
SC4000
Frame Boundary Latch Set Delay Enable
(C_52) (Read/Write)
0 -> Frame Boundary Latch Set at frame
boundary - no delay (Default)
1 -> Frame Boundary Latch Set is
delayed until after the input buffer to
output buffer transfer is complete (4
internal clocks after frame boundary).
Note 1
: With direct W/R to Parallel Ac-
cess Register Enabled (C_11=1), using
the delayed frame boundary interrupt
indicates that it is now safe to read from
and write to the Parallel Access Regis-
ters. To avoid data corruption, all access
must be completed 8 internal clocks
prior to the next delayed frame bound-
ary interrupt.
Note 2:
The internal clock is equal to
either the SCbus data rate or the Local
bus data rate whichever is faster.
INT_0 Mask_N (C_53) (Read/Write)
Clearing this bit(“0”) masks INT_0.
INT_0 is the logical OR of CLKFAIL
(C_56), Frame Boundary (C_57), Inter-
nal Master PLL Error (C_58) Latches
and SCbus Error (C_59) Indicator.
0 -> INT_0 Masked (Default)
1 -> INT_0 Enabled
Note
: The INT_0 Mask bit can be used
to globally disable interrupt generation
while the state of the latches can con-
tinue to be polled through the micro-
processor interface. This bit can also be
used to create edge-triggered interrupts.
INT_0 Output Polarity (C_54) (Read/Write)
0 -> INT_0 Active Low (Default)
1 -> INT_0 Active High
INT_0 Output Driver (C_55) (Read/Write)
0 -> Open Collector INT_0 Output
Driver (Default)
1 -> Totem-Pole INT_0 Output Driver
Configuration Register Byte 7, IAR = 07H
SCbus CLKFAIL Latch (C_56) (Read Only)
0 -> SCbus CLKFAIL Latch Clear
1 -> SCbus CLKFAIL Latch Set
Frame Boundary Latch (C_57) (Read only)
0 -> Frame Boundary Latch Clear
1 -> Frame Boundary Latch Set
Internal Master PLL Error Latch (C_58)
(Read Only)
This latch is set when the Internal Mas-
ter PLL is not “l(fā)ocked” to its selected ref-
erence.
0 -> Internal Master PLL Error Latch
Clear
1 -> Internal Master PLL Error Latch Set
SCbus Error Indicator (C_59) (Read Only)
C_59 is the logical OR of C_[67:64],
C_[74:72] and C_[83:80].
0 -> All SCbus Error Latches Clear
1 -> one or more SCbus Error Latches
Set
SCbus CLKFAIL Latch Clear_N (C_60)
(Read/Write)
0 -> SCbus CLKFAIL Latch held clear
(Default)
1 -> SCbus CLKFAIL Latch enabled
Frame Boundary Latch Clear_N (C_61)
(Read/Write)
0 -> Frame Boundary Latch held clear
(Default)
1 -> Frame Boundary Latch enabled
Internal Master PLL Error Latch Clear_N
(C_62) (Read/Write)
0 -> Internal Master PLL Error Latch
held clear (Default)
1 -> Internal Master PLL Error Latch
enabled
Configuration Register Byte 8, IAR = 08H
SCbus SCLKX2N Error Latch (C_64)
(Read Only)
The SCbus SCLKX2N Error Latch is
set when SCLKX2N does not transition
during the equivalent Master PLL clock
period.
0 -> SCbus SCLKX2N Error Latch Clear
1 -> SCbus SCLKX2N Error Latch Set
LBDR_[7:0]
C_[63:56]
Definition
0
56
SCbus CLKFAIL Latch
(Read only)
1
57
Frame Boundary
Latch (Read only)
2
58
Internal Master PLL
Error Latch
(Read only)
3
59
SCbus Error Indicator
(Read only)
4
60
SCbus CLKFAIL Latch
Clear_n
5
61
Frame Boundary
Latch Clear_n
6
62
Internal Master PLL
Error Latch Clear_n
7
63
Reserved (0)
(Read only)
LBDR_[7:0]
C_[71:64]
Definition
0
64
SCbus SCLKX2N
Error Latch
(Read only)
1
65
SCbus SCLKX2NA
Error Latch
(Read only)
2
66
SCbus SCLK Error
Latch (Read only)
3
67
SCbus SCLKA Error
Latch (Read only)
4
68
SCbus SCLKX2N
Error Latch Clear_n
5
69
SCbus SCLKX2NA
Error Latch Clear_n
6
70
SCbus SCLK Error
Latch Clear_n
7
71
SCbus SCLKA Error
Latch Clear_n
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| SC4002A | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:LCD MODULES SC4002A ( 40 CHARACTERS x 2 LINES ) |
| SC4002ALM-6 | 功能描述:AMPLIFIER TRIP UNIVERSAL INPUT D 制造商:cynergy 3 系列:SC 零件狀態(tài):在售 類型:過程感應(yīng) 跳脫狀態(tài):通電高/低 跳脫范圍:- 延遲時間:無延遲 電壓 - 電源:16 ~ 30VDC 輸出類型:繼電器 電路:SPDT（1 C 形） 不同電壓時的觸頭額定電流:3A @ 240VAC 安裝類型:DIN 軌道 工作溫度:0°C ~ 55°C 標準包裝:1 |
| SC4004 | 制造商:Ferraz Shawmut 功能描述: |
| SC4004A | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:LCD MODULES 40 CHARACTERS x 4 LINES |
| SC4004B | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:40 CHARACTERS x 4 LINES |
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