參數(shù)資料
型號(hào)： SC4000
廠商： NXP SEMICONDUCTORS
元件分類： 路由/交換
英文描述： Pressure Transducer, Series 19 mm, Compensated, Pressure Range: 0 psi to 200 psi, Vacuum Gage, 1/8-27 NPT, 10 Vdc excitation
中文描述： TELECOM, DIGITAL TIME SWITCH, PQFP100
封裝： TQFP-100
文件頁數(shù)： 27/52頁
文件大小： 179K
代理商： SC4000
2000 Sep 07
27
Philips Semiconductors
Preliminary specification
Universal Timeslot Interchange
SC4000
CONFIGURATION REGISTERS
Configuration Register Byte 0, IAR = 00H
SCbus Clock Master (C_0) (Read/Write)
This bit is synchronized with the Master
Clock Input enables the SC4000 to start
and stop being SCbus Clock Master.
0-> SCbus Clock Master Disabled
(Default)
1-> SCbus Clock Master Enabled
Note:
With IAR=00H and LBDR D_0=0
issue Terminate command to asynchro-
nously stop being SCbus Clock Master
when no Master Clock Input is present
(i.e dead clock)
SCbus Clock Master Arm (C_1) (Read/Write)
The process of becoming SCbus Clock
Master can be sped up by arming the
SC4000 which is intended to become
clock master in the event of a clock fail-
ure. When a SC4000 is armed and CLK-
FAIL=1 the C_0 bit is automatically set.
The SC4000 begins driving the SCbus
within 4 clocks of CLKFAIL going high.
0-> SCbus Clock Master Disarmed
(Default)
1-> SCbus Clock Master Armed
Note
: C_51 SCbus CLKFAIL Debounce
Enable must be set to use this feature.
SCbus Primary/Alternate Select (C_2)
(Read/Write)
The SC4000 provides Alternate SCbus
signals for fault tolerance. This bit con-
trols internal signal selection.
0->Primary SCbus signals selected
(Default)
1->Alternate SCbus Signals selected
Diagnostic Mode Enable (C_3) (Read/Write)
In Diagnostic Mode the SC4000’s SCbus
output drivers and receivers are electri-
cally disconnected from the SCbus. In-
ternally, the SCbus outputs are looped
back to their corresponding inputs. This
creates a virtual SCbus within the
SC4000 that can be used to test thor-
oughly the SC4000 without disrupting
normal SCbus traffic.
0->Diagnostic Mode Disabled
1->Diagnostic Mode Enabled (default)
Note 1
: Diagnostic Mode is Enabled
when the SC4000 is reset.
Note 2:
A clock must be present at the
Master Clock input to use this mode.
SCbus Framing Mode [1:0](C_[5:4])
(Read/Write)
0x -> 2.048 Mb/s, 256 Bits/Frame, 32
Timeslots/Frame (Default)
10 -> 4.096 Mb/s, 512 Bits/Frame, 64
Timeslots/frame
11 -> 8.192 Mb/s, 1024 Bits/Frame, 128
Timeslots/Frame
Local bus Framing Mode [1:0](C_[7:6])
(Read/Write)
0x -> 2.048 Mb/s, 256 Bits/Frame, 32
Timeslots/Frame (Default)
10 -> 4.096 Mb/s, 512 Bits/Frame, 64
Timeslots/frame
11 -> 8.192 Mb/s, 1024 Bits/Frame,
128 Timeslots/Frame
Note
: If the Local Bus framing mode
selection is for a higher data rate than
that of the SCbus framing mode, then a
65.536 MHz clock must be provided on
X_IN.
Configuration Register Byte 1, IAR = 01H
Master Clock Input Frequency Select
[2:0] (C_[10:8]) (Read/Write)
000-> 2.048 MHz (Default)
001-> 4.096 MHz
010-> 8.192 MHz
011->16.384 MHz
100-> 32.768 MHz
101-> 65.536 MHz
110-> Reserved
111-> Reserved
Note
: The Master Clock Input may be
sourced from either X_IN or CLK_IN
(see C_43).
Direct R/W to Parallel Access Registers
Enable (C_11) (Read/Write)
0-> Direct R/W Disabled (Default)
1-> Direct R/W Enabled
Note
: When Disabled A_[8:2] is don’t
care. When Enabled address setup to
falling edge of WR_N or STRB_N is
required.
Message Channel Registered TXD Enable
(
C_12) (Read/Write)
0-> TXD Passed Through onto MC
(Default)
1-> TXD Registered onto MC
LBDR_[7:0]
C_[7:0]
Definition
0
0
SCbus Clock Master
1
1
SCbus Clock Master
Arm
2
2
SCbus Primary/
Alternate Select
3
3
Diagnostic Mode
Enable
[5:4]
[5:4]
SCbus Framng Mode
[1:0]
[7:6]
[7:6]
Local Bus Framng
Mode [1:0]
LBDR_[7:0]
C_[15:8]
Definition
[2:0]
[10:8]
Master Clock Input
Frequency Select [2:0]
3
11
Direct R/W to Parallel
Access Registers
Enable
4
12
Message Channel
Registered TXD Enable
5
13
Message Channel
TXD_0 or TXD_1
(internal HDLC) Select
6
14
Message Channel
Clock Duty Cycle
Select
7
15
Message Channel
Output Disable
(w/Loopback)
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