參數(shù)資料
型號(hào)： SC4000
廠商： NXP SEMICONDUCTORS
元件分類： 路由/交換
英文描述： Pressure Transducer, Series 19 mm, Compensated, Pressure Range: 0 psi to 200 psi, Vacuum Gage, 1/8-27 NPT, 10 Vdc excitation
中文描述： TELECOM, DIGITAL TIME SWITCH, PQFP100
封裝： TQFP-100
文件頁(yè)數(shù)： 15/52頁(yè)
文件大?。?/td> 179K
代理商： SC4000
2000 Sep 07
15
Philips Semiconductors
Preliminary specification
Universal Timeslot Interchange
SC4000
Figure 3 shows an external master PLL
implementation. The SC4000 provides
the 8 KHz reference output signal
REF_8K_OUT (pin 7) to the external
PLL. This 8 KHz reference signal is
sourced from either REF_8K[1:0] or
SREF_8K. The output of the external
PLL is then routed back to the SC4000
via CLK_IN (pin 6). The master clock
input (CLK_IN) frequency select at
C_[10:8] would then be programmed
for the external PLL frequency.
As shown in Figure 4, the SC4000 also
provides an internal clock PLL and local
bus PLL timing control circuitry for
both SCbus master and slave operations.
The internal clock PLL is used to create
the 4.096 or 8.192 MHz timing slaved to
the SCbus when the local bus is running
faster than the SCbus (i.e., 2.048 MHz at
SCbus, 8.096 MHz at local bus). If the
SCbus is faster or equal to the local bus,
then the SCbus clocks serve as the inter-
nal clock and use to create the local bus
clocks as well as message channel clock.
The local bus clock PLL is used to create
a 2.048 MHz L_CLK when:
Local bus framing mode C_[7:6] is set
to 2.048 Mb/s
A 65.536 MHz clock is supplied on
X_IN
The C_29 bit is set to one.
If SCLK stops transitionally such as
during a clock fail condition (CLKFAIL
= 1), then the local bus clock PLL runs
free to generate L_CLK clock. In addi-
tion, the local bus SO lines are tri-stated
so that the network interface can con-
tinue to run.
Interrupts Control
The SC4000 can interrupt the host CPU
with the interrupt request signal INT_0
(pin 14). This signal is configured and
unmasked by configuration register bits
C_55, C_54 and C_53. The interrupt
sources are:
C_56 SCbus CLKFAIL
C_57 Frame Boundary
C_58 Internal Master PLL Error
C_59 SCbus Error Indicator (logical
“OR” of C_[67:64], C_[74:72], and
C_[83:80])
The interrupts are structured this way to
improve performance by allowing a sin-
gle read operation (of configuration reg-
ister byte 7) to determine whether the
SC4000 is the source of the interrupt.
Each of the SC4000 interrupt sources
can be individually masked.
Figure 3. External Master PLL (C_43 = 1) Function Block
C_0, C_3, C_[23:22]
SCLKX2N
SCLKX2NA
SCLK
SCLKA
46, 47
49, 50
SREF_8K
SREF_8KA
51, 52
REF_8K_[1:0]
C_[42:40]
C_[45:44]
C_3, C_23, C_46
Master PLL
Reference
8 K Select
SCbus
SREF_8K
Source
Select
4, 5
FSYNCN
FSYNCNA
54, 55
Programmable
Divider
C_[10:8], C_[5:4]
To Internal Watchdogs and
SCbus Error Detectors
C_2
Primary
or
Alternate
Select
External
PLL
C
6
R
7
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參數(shù)描述
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