參數(shù)資料
型號： SC4000
廠商： NXP SEMICONDUCTORS
元件分類： 路由/交換
英文描述： Pressure Transducer, Series 19 mm, Compensated, Pressure Range: 0 psi to 200 psi, Vacuum Gage, 1/8-27 NPT, 10 Vdc excitation
中文描述： TELECOM, DIGITAL TIME SWITCH, PQFP100
封裝： TQFP-100
文件頁數(shù)： 28/52頁
文件大?。?/td> 179K
代理商： SC4000
2000 Sep 07
28
Philips Semiconductors
Preliminary specification
Universal Timeslot Interchange
SC4000
Note:
When C_12=0 the HDLC Con-
troller must be programmed to output
TXD on the Rising edge of MC_CLK.
When C_12=1 the HDLC controller
must be programmed to output TXD on
the falling edge of MC_CLK.
Message Channel TXD_0 or TXD_1 Select
(C_13) (Read/Write)
0-> TXD_0 External HDLC Controller
(Default)
1-> TXD_1 Future Internal HDLC
Controller
Note:
If TXD_1 is selected on an SC4000
without an Internal HDLC Controller
all 1’s will be output on MC (idle).
Message Channel Clock Duty Cycle Select
(C_14) (Read/Write)
0-> 50% (Default)
1-> 75% (2 &4 Mb/s SCbus modes),
62.5% (8 Mb/s SCbus)
Note
: SCLKX2N must be present to
select 75% when SCbus is 2 Mb/s.
Message Channel Output Disable
(W/ loopback) (C_15) (Read/Write)
0-> Message Channel Output Enabled
(Default)
1-> Message Channel Output Disabled
Note:
When the Message Channel is Dis-
abled, TXD is looped back to the RXD to
allow diagnostics runs on the HDLC
Controller.
Configuration Register Byte 2, IAR = 02H
SCbus SD Sample Position (C_16)
(Read/Write)
0-> Sample at 50% of Bit Cell (Default)
1-> Sample at 75% of Bit Cell
Note
: SCLKX2N must be present to
select 75% sample.
Local Bus SI Sample Position (C_17)
(Read/Write)
0-> Sample at 50% of Bit Cell (Default)
1-> Sample at 75% of Bit Cell
Note 1:
To select 75% sample,SCLKX2N
must be present or the local bus framing
mode must be set to a data rate that is ei-
ther higher or lower than the SCbus
framing mode.
Note 2:
To select 75% sample (C_17=1),
it is not necessary to select the L_CLK
rate equal to 2X (C_28=1)
SCbus SD Output Delay Enable (C_18)
(Read/Write)
To avoid bus contention, enabled SCbus
SD outputs are delayed when coming
out of tri-state.
0-> SCbus SD Output Delay Disabled
(Default)
1-> SCbus SD Output Delay Enabled
Local bus SO Output Delay Enable (C_19)
(Read/Write)
To avoid bus contention, enabled local
bus SO outputs are delayed when com-
ing out of tri-state.
0-> Local bus SO Output Delay Dis-
abled (Default)
1-> Local bus SO Output Delay Enabled
SCbus FSYNCN Sample Position (C_20)
(Read/Write)
0-> Sample at rising edge of SCLK
(Default)
1-> Sample at rising edge of SCLKX2N
with SCLK high.
SCbus FSYNCN Rate (C_21) (Read/Write)
This bit determines the clock by which
the FSYNCN signal is generated.
0 -> 1 SCLK period (Default)
1 -> 1 SCLKX2N period
Note
: This mode is provided for MVIP
compatibility.
SCbus SCLKX2N, SCLKX2NA Output
Disable(C_22) (Read/Write)
This bit disables the SCLKX2N and
SCLKX2NA outputs when they are not
required. When disabled, the outputs
are tri-stated.
0-> SCLKX2N and SCLKX2NA Outputs
Enabled (Default)
1-> SCLKX2N and SCLKX2NA Outputs
Disabled
LBDR_[7:0] C_[23:16] Definition
0
16
SCbus SD Sample
Position
1
17
Local bus SI Sample
Position
2
18
SCbus SD Output
Delay Enable
3
19
Local bus SO Output
Delay Enable
4
20
SCbus FSYNCN
Sample position
5
21
SCbus FSYNCN Rate
6
22
SCbus SCLKX2N,
SCLKX2NA Output
Disable
7
23
SCbus Alternate (A)
Signals Output Enable
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