
2000 Sep 07
33
Philips Semiconductors
Preliminary specification
Universal Timeslot Interchange
SC4000
SCbus SREF_8K NE SREF_8KA Error Latch
(C_80)(Read only)
The SCbus SREF_8K NE SREF_8KA
Error Latch is set when SREF_8K and
SREF_8KA are not equal for three
consecutive Master PLL clocks.
0 ->SCbus SREF_8K NE SREF_8KA
Error Latch Clear
1 ->SCbus SREF_8K NE SREF_8KA
Error Latch Set
SCbus CLKFAIL NE CLKFAILA Error Latch
(C_81)(Read only)
The SCbus CLKFAIL NE CLKFAILA
Error Latch is set when CLKFAIL and
CLKFAILA are not equal for three
consecutive Master PLL clocks.
0 ->SCbus CLKFAIL NE CLKFAILA
Error Latch Clear
1 ->SCbus CLKFAIL NE CLKFAILA
Error Latch Set
SCbus MC NE MCA Error Latch (C_82)
(Read only)
The SCbus MC NE MCA Error Latch
is set when MC and MCA are not
equal. MC_CLK is used to sample
the comparison.
0 ->SCbus MC NE MCA Error Latch
Clear
1 ->SCbus MC NE MCA Error Latch Set
SCbus SD Error Indicator (C_83) (Read only)
C_83 is the logical OR of C_[103:88]
0 -> All SCbus SD Error Latches Clear
1 -> One or more SCbus SD Error Latch
Set
SCbus SREF_8K NE SREF_8KA Error Latch
Clear_N (C_84)(Read/Write)
0 ->SCbus SREF_8K NE SREF_8KA
Error Latch held clear (Default)
1 ->SCbus SREF_8K NE SREF_8KA
Error Latch enabled
SCbus CLKFAIL NE CLKFAILA Error Latch
Clear_N (C_85)(Read/write)
0 ->SCbus CLKFAIL NE CLKFAILA
Error Latch held clear (Default)
1 ->SCbus CLKFAIL NE CLKFAILA
Error Latch enabled
SCbus MC NE MCA Error Latch Clear_N
(C_86)(Read/Write)
0 ->SCbus MC NE MCA Error Latch
held clear (Default)
1 ->SCbus MC NE MCA Error Latch
enabled
SCbus SD Error Latch Clear_N
(C_87)(Read/Write)
0 ->SCbus SD Error Latch held clear
(Default)
1 ->SCbus SD Error Latch enabled
Note
: C_87 controls all 16 SD Error
latches.
Configuration Register Byte 11, IAR = 0BH
Configuration Register Byte 12, IAR = 0CH
SCbus SD_[15:0] Error Latch (C_[103:88])
(Read only)
An SCbus SD Error Latch is set when an
SD output timeslot is enabled and the
internally generated SD signal and
SCbus are not equal. This feature is
provided to detect when more than one
SCbus device is enabled on the same
timeslot. All SCbus SD Error Latches
are enabled and cleared by C_87.
Note:
If multiple destination channels
within the same SC4000 are enabled
onto the same timeslot anerror will not
occur. Bus contention is prevented by
logically “ANDing” the internal SD
signals before they are output onto the
SCbus SD.
SUMMARY OF SC4000
CONFIGURATION REGISTERS
Mscellaneous
Diagnostic Mode Enable (C_3)
(Read/Write)
Direct R/W to Parallel Access Registers
Enable (C_11) (Read/Write)
SC4000 Revision/Version Register
(C_[39:32]) (Read only)
Master Clock/PLL
Master Clock Input Frequency Select
[2:0] (C_[10:8]) (Read/Write)
Master PLL Reference Select [2:0]
(C_[42:40]) (Read/Write)
Internal/External Master PLL Select
(C_43) (Read/Write)
SCbus (MVIP Bus)
SCbus Clock Master (C_0)
(Read/Write)
Scbus Clock Master Arm (C_1)
(Read/Write)
SCbus Primary/Alternate Select (C_2)
(Read/Write
SCbus Framing Mode [1:0](C_[5:4])
(Read/Write)
SCbus SD Sample Position (C_16)
(Read/Write)
SCbus SD Output Delay Enable (C_18)
(Read/Write)
SCbus FSYNCN Sample Position
(C_20) (Read/Write)
SCbus FSYNCN Rate (C_21)
(Read/Write)
SCbus SCLKX2N, SCLKX2NA Output
Disable (C_22) (Read/Write)
SCbus Alternate (“A”) Signals Output
Enable (C_23) (Read/Write)
SCbus SREF_8K Source Select [1:0]
(C_[45:44]) (Read/Write
SCbus SREF_8K Output Enable (C_46)
(Read/Write)
SCbus SCLK 8.192 MHz 62.5% Duty
Cycle (C_47) (Read/Write)
LBDR_[7:0]
C_[95:88]
Definition
[7:0]
[95:88]
SCbus SD_[7:0]
Error Latch (Read
only)
LBDR_[7:0]
C_[103:96]
Definition
[7:0]
[103:96]
SCbus SD_[15:8]
Error Latch
(Read only)