參數(shù)資料
型號: SAA7381
廠商: NXP SEMICONDUCTORS
元件分類: 消費家電
英文描述: ATAPI CD-R block decoder
中文描述: SPECIALTY CONSUMER CIRCUIT, PQFP144
文件頁數(shù): 92/108頁
文件大小: 380K
代理商: SAA7381
1997 Aug 12
92
Philips Semiconductors
Objective specification
ATAPI CD-R block decoder
SAA7381
11.3
Sub-CPU interface timing
Table 111
Timing parameter values for Figs 28 and 29
Note
1.
t
CLCL
= the SAA7381 system clock period.
SYMBOL
PARAMETER
MIN.
MAX.
UNIT
t
AVLL
t
RLDV
t
W(ALE)
t
h(A)
t
DVWL
address valid to ALE LOW
RD LOW to valid data in
ALE pulse width
address hold time
DATA valid before WR LOW
10
35
10
0
7t
CLCL
+ 20
(1)
ns
ns
ns
ns
ns
Fig.27 Host terminating a DMA burst during a write command.
handbook, full pagewidth
MGK532
DRQ (drive)
DACKb (host)
STOP (host)
DMARDYb (drive)
STROBE (host)
DATA (host)
DA and CS
CRC
tli
tli
tli
tli(min)
tsu(DV)
th(DV)
t(IORDY)(max)
tsu(ass/deass)
tsu(ass/deass)
tsu(ass/deass)
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