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參數(shù)資料
| 型號： | SAA7381 |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 消費家電 |
| 英文描述： | ATAPI CD-R block decoder |
| 中文描述： | SPECIALTY CONSUMER CIRCUIT, PQFP144 |
| 文件頁數(shù)： | 52/108頁 |
| 文件大?。?/td> | 380K |
| 代理商： | SAA7381 |
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1997 Aug 12
52
Philips Semiconductors
Objective specification
ATAPI CD-R block decoder
SAA7381
7.5.10
G
ENERIC INTERFACE OPERATION
Implementation of the generic interface with the
NCR 53CF92 in a multiplexed bus configuration is shown
in Fig.4. The host interface, after power-up, needs to be
configured for the SCSI controller by writing the value 3 to
the RESET register (address FF86H) for an 8-bit data
transfer configuration and the value 4 for a 16-bit data
transfer configuration. The NCR 53CF92 device is
configured by tying it’s mode pin to ground. In this mode
the NCR 53CF92 device expects from the microcontroller
a multiplexed address/data bus. Multiplexed address/data
bus is the only mode supported by the SAA7381.
The active LOW Chip Select (CS) signal from the
SAA7381 is generated by the host interface. There are
32 specific SCSI addresses in the SAA7381 memory map,
between location FFC0H and FFDFH. The CS pin will be
active LOW for addresses in this range. The standard
register set on the NCR 53CF92 contains 16 registers
which are accessed when the CS is true. The specific
register being accessed is determined by the states of the
RD and WR signals together with the address pins
A3 to A0.
Fig.4 Generic interface connection to NCR 53CF92 in multiplexed mode.
handbook, full pagewidth
MGL175
NCR 53CF92
DREQ
DACK
DBWR
DB7 to DB0
A0
A1
A2/DBRD
A3/ALE
CS
RD
WR
MODE
SAA7381
DMACK/DMARQ
DMARQ/DMACK
DD0 to DD7
MICROCONTROLLER
DA1/DBWR
DA2/DBRD
CS0/SCSICS
8051
8-bit address/data bus
8-bit DMA bus
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