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參數(shù)資料
| 型號(hào)： | SAA7381 |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 消費(fèi)家電 |
| 英文描述： | ATAPI CD-R block decoder |
| 中文描述： | SPECIALTY CONSUMER CIRCUIT, PQFP144 |
| 文件頁數(shù)： | 34/108頁 |
| 文件大?。?/td> | 380K |
| 代理商： | SAA7381 |
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1997 Aug 12
34
Philips Semiconductors
Objective specification
ATAPI CD-R block decoder
SAA7381
Table 54
Description of the interrupt register bits
REGISTER
INTERRUPT
DESCRIPTION
INTERRUPT 1 dec
block by block decoder interrupt
ERCO cannot be started on current block
one or more bytes coming from CD-DSP have been flagged with error
corrected current block.
one or more bytes remain in error
bad CRC on current block
bad Q CRC on current block
indicates that interrupt is caused by an enabled interrupt from INT2
the host counter decremented to zero and may have been reloaded; requires
sub-CPU intervention when reload is disabled
drive processing pointers have reloaded
the host reload count decremented to zero; no more host reloads are available
copy process has finished
subcode receive block detection of early subcode 98 frame sync period
asserts when ‘dmacount’ reaches zero with ‘dmaon’ bit set
indicates that interrupt is caused by an enabled interrupt from INT1
indicates that the interrupt is from the UART interrupt register
UART COMSYNC pin rising edge interrupt
SYSSYNC pin rising edge interrupt
COMSYNC falling edge interrupt
SYSSYNC pin falling edge interrupt
transmit buffer has become empty
receive buffer has become full
receive buffer has overrun
a character has been received with illegal parity
nocor
erablk
cblk
uceblk
crc-ng
q-ng
int2
INTERRUPT 2 hostbytecountzero
drivereload
hostcursegcntzero
copyend
subcode syncint
dmatxint
int1
uartint
comsync
syssync
notcomsync
notsyssync
nottxbfull
rxbfull
overrun
rxparity
UART INT
7.5
Host interface
7.5.1
I
NTRODUCTION
The SAA7381 host interface block is responsible for the
transfer of data and control information between the
memory processor, external host and microcontroller.
The host interface operates in conjunction with the
SAA7381 Auxiliary block (Aux block). The Aux block
contains several registers that automate the SAA7381
memory processor in its task of supplying the host
interface with data from the buffer memory and receiving
data from the host interface to be placed in the buffer
memory. The host interface automates data transfer to
and from the host, whereas the Aux block automates data
transfer, via the memory processor and buffer memory,
depending on the CD format.
The host interface features are as follows:
Supports ATA Packet Interface (ATAPI revision 2.6) for
CD-ROMs
Supports ATA/ATAPI 16-bit PIO data transfers for
Modes 0, 1, 2, 3 and 4
Supports ATA/ATAPI single/multi word DMA transfers
for Modes 0, 1 and 2
Supports ultra DMA for Mode 0
Supports generic interface connection to external SCSI
controller device (NCR 53CF92)
Command and status registers of external generic
interface controller are optionally mapped via the host
interface pins of the SAA7381. The SAA7381 becomes
the bus master.
Operates automatically with multi-block host data
transfers
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