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參數(shù)資料
| 型號： | SAA7381 |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 消費家電 |
| 英文描述： | ATAPI CD-R block decoder |
| 中文描述： | SPECIALTY CONSUMER CIRCUIT, PQFP144 |
| 文件頁數(shù)： | 35/108頁 |
| 文件大?。?/td> | 380K |
| 代理商： | SAA7381 |
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1997 Aug 12
35
Philips Semiconductors
Objective specification
ATAPI CD-R block decoder
SAA7381
Reduces microcontroller load in simple streaming
transfers to or from host using a circular buffer
Recognizes ATA SRST, the ATAPI reset command
(0X08) and the ATAPI packet command (0XA0) and
handles these automatically in ATAPI mode
Handles unexpected ATA commands during PIO data
transfers
Provides automatic DRQ for all PIO data transfers
Provides automatic detection of ATAPI packet (A0)
command and reception of the packet bytes
Provides automatic completion sequence for PIO DMA
and ultra DMA transfers
Supports shadowing of registers for single drive
configurations with non-existent slave.
7.5.2
D
ESCRIPTION OF THE HOST INTERFACE BLOCK
The host interface block consists of three FIFOs which can
be configured by the DTCTR register to generate the
required data path through the host interface block.
The design supports ATAPI (revision 2.6) for CD-ROM
interfaces.
The host interface has a shadow status register to permit
proper ATA operation. The PDIAG and DASP signals are
controlled by the register bits in the host interface block.
The microcontroller has access to all registers in the host
interface block. The microcontroller can control all
operations required for data transfer to and from the host,
but may configure the host interface sequencer to
automate the following three operations:
1.
Automation of detection of the A0 packet command
and reception of the 12-byte packet.
2.
Automation of the data transfer sequences for PIO,
DMA and ultra DMA modes of data transfer.
3.
Automation of completion sequences for PIO, DMA
and ultra DMA modes of data transfer.
The host interface provides a generic interface mode for a
glueless connection to an external SCSI controller device.
In this mode the microcontroller can configure the registers
of the SCSI controller device and initiate DMA transfers.
7.5.2.1
The SAA7381 host interface ATAPI registers visible to the host
Table 55
Host interface registers as seen from the host (note 1)
Note
1.
The operation of these registers complies with the ATA-3 specification (revision 6) and the ATAPI specification
(revision 2.6).
CS0
1
1
0
0
0
0
0
0
0
0
0
0
CS1
0
0
1
1
1
1
1
1
1
1
1
1
DA2
1
1
0
0
0
0
0
1
1
1
1
1
DA1
1
1
0
0
0
1
1
0
0
1
1
1
DA0
0
1
0
1
1
0
1
0
1
0
1
1
HOST READ (DIOR)
ALT STATUS: alternative status
ADRADR: ATAPI drive address
DATA: data register
AERR: ATAPI error register
SHERR: ATAPI error register (shadow) unused
AINTR: ATAPI interrupt reason register unused
ASAMT: ATAPI SAM TAG register
DBCL: ATAPI byte count low
DBCH: ATAPI byte count high
ADRSEL: ATAPI drive select register
ASTAT: ATAPI status register
SHSTAT: ATAPI status register
(shadow)
HOST WRITE (DIOW)
ADCTRL: ATAPI device control
not used
DATA: data register
AFEAT: ATAPI features register
ASAMT: ATAPI SAM TAG register
DBCL: ATAPI byte count low
DBCH: ATAPI byte count high
ADRSEL: ATAPI drive select register
ACMD: ATAPI command register
unused
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