參數(shù)資料
型號： SAA7381
廠商： NXP SEMICONDUCTORS
元件分類： 消費家電
英文描述： ATAPI CD-R block decoder
中文描述： SPECIALTY CONSUMER CIRCUIT, PQFP144
文件頁數(shù)： 61/108頁
文件大小： 380K
代理商： SAA7381
1
6
P
O
A
S
If (transmit register empty)
end if;
Transmission will automatically stop when the ‘uart_dma_ctrl’ (bits 5 to 0) (the ‘txdmacount’) has incremented to zero. This condition will produce the
interrupt.
Data transmission rates are selectable by writing a value n(0 to 255) to the UART_PRE_SCALER register. The baud rate for each mode can then be
calculated as follows:
For the SPI mode
For the S2B mode
Table 93
UART general registers
Notes
1.
2.
See Table 95.
See Table 96.
ADDRESS
FF28H
FF29H
FF4AH
FF4BH
FF4CH
FF4DH
FF74H
FF75H
FF76H
NAME
BIT 7
bit 15
bit 7
bit 15
bit 7
bit 15
bit 7
BIT 6
bit 14
bit 6
bit 14
bit 6
bit 14
bit 6
BIT 5
bit 13
bit 5
bit 13
bit 5
bit 13
bit 5
BIT 4
bit 12
bit 4
bit 12
bit 4
bit 12
bit 4
BIT 3
bit 11
bit 3
bit 11
bit 3
bit 11
bit 3
BIT 2
bit 10
bit 2
bit 10
bit 2
bit 10
bit 2
BIT 1
bit 9
bit 1
bit 9
bit 1
bit 9
bit 1
BIT 0
bit 8
bit 0
bit 8
bit 0
bit 8
bit 0
AUXSEGMENT-H
AUXSEGMENT-L
SPI_RX_OFF-H
SPI_RX_OFF-L
SPI_TX_OFF-H
SPI_TX_OFF-L
UART_PRE_SCALER (rw)7
UART_DMA_CTRL (rw)
UARTCOM (w)
prescale value (bits 7 to 0)
rcvdma on
paron
txdma on
spion
txdmacount (bits 5 to 0)
parpol
clkpol
d0
d0
rvparity
rvparity
rxparity
FF77H
FF7H
FF78H
FF79H
FF7EH
FF7FH
RXDATA (w)
RXDATA (r)
d7
d7
d6
d6
d5
d5
d4
d4
d3
d3
d2
d2
d1
d1
UARTTINTSTAT/RESET (rw)
UARTTINTEN (w)
UARTSTAT (r)
(1)
UARTAUXSTAT (r)
(2)
comsync
comsyn
comsync
comiack
syssync
syssync
syssync
txfull
not comsync
not comsync
comsync
rxfull
not syssync
not syssync
syssync
not txbfull
not txbfull
txbfull
rvbfull
rvbfull
rxbfull
overrun
overrun
overrun
TRANSMITREG
RAM [AUXSEGMENT
2560
SPI_TX_OFFSET]
+
×
=
SPI_TX_OFFSET
SPI_TX_OFFSET
1
+
=
uart_dma_ctrl (5 : 0)
uart_dma_ctrl (5 : 0)
1
–
=
f
SPI
f
1
+
)
]
--2
=
f
S2B
f
16
n
1
+
)
[
]
---------------------------------------
=
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