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參數(shù)資料
| 型號： | SAA7381 |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 消費家電 |
| 英文描述： | ATAPI CD-R block decoder |
| 中文描述： | SPECIALTY CONSUMER CIRCUIT, PQFP144 |
| 文件頁數(shù)： | 54/108頁 |
| 文件大?。?/td> | 380K |
| 代理商： | SAA7381 |
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1997 Aug 12
54
Philips Semiconductors
Objective specification
ATAPI CD-R block decoder
SAA7381
Fig.6 Burst DMA mode using multiplexed bus configuration.
handbook, full pagewidth
MGK515
DMACK
DBRD/
DBWR
7.6
Microcontroller interface
This section provides a brief introduction to the software
and hardware environment expected in a system using the
SAA7381 device. Because all of the SAA7381 registers
are randomly accessible, the processor controlling the
SAA7381 is able to use interrupts.
7.6.1
K
ERNEL BASED FIRMWARE
It is recommended that the sub-CPU runs a multi-tasking
kernel to properly support the multiple ‘threads’ of
operation that are required of it in use. Therefore the
memory mapper specified in this document has the
concept of having 2 pages of memory for data. Then one
page of data space can be switched in to the memory map
for each thread as needed, while still keeping a fixed part
of the memory map for the interrupt service routines and
other fixed housekeeping code and data.
7.6.2
16-
BIT REGISTERS AUTOMATIC READ AND WRITE
All of the 16-bit registers provided in the SAA7381, are
used by writing the Most Significant Bit (MSB) first. These
registers are located in the address range FF20H to
FF6FH together with some 8-bit registers. To facilitate
‘snapshot’ reading or writing of the 16-bit register an 8-bit
holding register is provided to store the ‘spare’ byte of
data.
This is implemented in such a way that a 16-bit read
consists of a sample of the value of the register at the
instant that the high byte was read from that register.
The low byte is kept in a holding register and presented to
the sub-CPU when the low byte is requested. Even if the
sub-CPU is interrupted (and the holding register is then
stacked and replaced during the service routine) the 16-bit
read will be the value of the register at a single instance in
time.
Similarly for writing, the high byte is held in the holding
register to be written later to the 16-bit register at the same
time as the low byte is written to the SAA7381. Again the
holding register must be saved during an Interrupt Service
Routine (ISR) if the ISR itself is likely to cause any 16-bit
reads or writes to take place. It should be noted that any
ISR, which requires access to a 16-bit or 8-bit register in
the address range FF20H to FF6FH, will overwrite the
holding register and therefore its contents must be stacked
before the interrupt is serviced. Furthermore, there is only
one holding register that may be accessed both for reading
and writing. In this way the interrupt routine can easily save
data that was stored in the holding register before it was
written.
A single location (TEMP_DATA, register FF6FH) is used
as the location to read the value of the holding register,
regardless of which address was used in the original read
or write process. The IRS stacking process of the holding
register is illustrated in Fig.8.
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