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參數(shù)資料
| 型號： | SAA7381 |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 消費(fèi)家電 |
| 英文描述： | ATAPI CD-R block decoder |
| 中文描述： | SPECIALTY CONSUMER CIRCUIT, PQFP144 |
| 文件頁數(shù)： | 83/108頁 |
| 文件大?。?/td> | 380K |
| 代理商： | SAA7381 |
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1997 Aug 12
83
Philips Semiconductors
Objective specification
ATAPI CD-R block decoder
SAA7381
11.2.3
U
LTRA
DMA
OPERATION AND TIMING
Selection of ultra DMA is similar to multi-word DMA operation. Bits 5, 6 and 7 of the DTCTR register should all be set to
logic 1 and data byte counts and data flow selection does not change from ATAPI DMA operation.
The ‘ultra_stop’ interrupt (IFSTAT bit 4) when enabled by ‘ultra_stopien’ (IFCTRL bit 4) will interrupt the microcontroller
if the host stops a transfer before the required data has been transfer i.e. the data byte count has not reached zero.
A flag, ‘crc_error’ (IFSTAT bit 0) if asserted in conjunction with the ‘dtei’ interrupt (IFSTAT bit 6) will indicate to the
microcontroller that the last transfer of data was corrupt.
No changes of pin direction are required for ultra DMA, but the ATA description changes (see Table 109).
Table 109
Ultra DMA pin changes
11.2.4
U
LTRA
DMA
READ
/
WRITE TIMING
This section provides the timing diagrams for the ultra DMA protocol. The timing diagrams are shown in Figs 18 to 26.
The timing information is provided in Table 110.
Table 110
Timing parameter values; see Figs 18 to 26
ATA PIN NAME ULTRA DMA READ PIN NAME ULTRA DMA WRITE PIN NAME
COMMENT
IORDY
sender strobe
D_DMARDY
(device DMA ready)
DMARQ
DMACK
D_DMARDY can be used to
pause transmission
similar to ATAPI DMA
similar to ATAPI DMA, but also
used at the end of transmission
for the CRC strobe
stop can terminate the data
transfer before all bytes have
been transferred; this action will
generate a microcontroller
interrupt
H_DMARDY can be used by to
pause transmission
DMARQ
DMACK
DMARQ
DMACK
DIOR
STOP
sender strobe
DIOW
H_DMARDY (host DMA ready)
STOP
SYMBOL
PARAMETER
CONDITIONS
MIN.
MAX.
UNIT
T
cy
cycle time (from STROBE edge to STROBE
edge)
Mode 0
Mode 1
Mode 2
Mode 0
Mode 1
Mode 2
Mode 0
Mode 1
Mode 2
Mode 0
Mode 1
Mode 2
117
77
57
15
10
7
3
3
3
75
48
38
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
t
su(D)(RX)
data set-up time (at receiver)
t
h(D)(RX)
data hold time (at receiver)
t
su(DV)
data valid set-up time (at sender); time from data
bus being valid until STROBE edge
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