參數(shù)資料
型號: SAA7381
廠商: NXP SEMICONDUCTORS
元件分類: 消費家電
英文描述: ATAPI CD-R block decoder
中文描述: SPECIALTY CONSUMER CIRCUIT, PQFP144
文件頁數(shù): 27/108頁
文件大?。?/td> 380K
代理商: SAA7381
1997 Aug 12
27
Philips Semiconductors
Objective specification
ATAPI CD-R block decoder
SAA7381
7.3.3.1
Basic description of the multimedia output interface
The multimedia data output may be used either with an internal clock or an externally provided clock. The clock used
should be a correct multiple of 44100 Hz in order for the block to correctly output IEC 958.
The multimedia interface data FIFO is located in the block of segments associated with AUXSEGMENT master/slave
mode operation (see Fig.3).
Table 36
Description of the MMCTRL register bits
BIT
NAME
VALUE
0
1
0
1
00
01
10
DESCRIPTION
7
6
5
4
3
mmdiv
see Table 37
spdx2
I
2
S-bus output is single speed
I
2
S-bus (and IEC 958) output is double speed; video applications
I
2
S-bus bit clock is 64 times the sample rate
I
2
S-bus bit clock is 48 times the sample rate
multimedia internal clock is CRIN pin
multimedia internal clock is MCK pin
multimedia internal clock is system clock
2
wslen
1 and 0
mcksel
Fig.3 Master/slave mode operation.
handbook, full pagewidth
MGL179
e.g. DAC
slave: master = 0
SAA7381
e.g. DAC
master: master = 1
SAA7381
SCK
WS
SDO2
SCK
WS
SDO2
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