參數(shù)資料
型號(hào)： SAA7381
廠商： NXP SEMICONDUCTORS
元件分類： 消費(fèi)家電
英文描述： ATAPI CD-R block decoder
中文描述： SPECIALTY CONSUMER CIRCUIT, PQFP144
文件頁(yè)數(shù)： 43/108頁(yè)
文件大小： 380K
代理商： SAA7381
1997 Aug 12
43
Philips Semiconductors
Objective specification
ATAPI CD-R block decoder
SAA7381
Table 71
Description of the IFSTAT register bits
7.5.3.19
APCMD
During the ATAPI mode this register is used to read the packet command sent by the host. The packet command can
only be received if the appropriate mode has been selected (see DTCTR register; Table 62) and a data transfer has been
started (see DTRG register; see Table 56).
BIT
NAME
DESCRIPTION
7
cmdi
Command interrupt: in the ATAPI mode this bit is asserted when the PC host has written to
the ATAPI command register (see ACMD register; Section 7.5.3.15) and the drive is
selected. It is also asserted when the host writes the execute drive diagnostic command
(90H) to the ATAPI command register, regardless of whether the drive is selected. It is
negated when the microcontroller reads the ACMD register or writes logic 1 to ‘cmdi’.
Data transfer end interrupt: this bit is asserted at the end of data transfer. It is negated
when the microcontroller writes to the DTACK register or writes logic 1 to ‘dtei’. If the ATAPI
mode is selected this bit is also asserted when a packet command has been received and
after a microcontroller memory transfer. The interrupt generated by this bit can be masked
by the auto sequencer.
Auto sequencer data request interrupt: if enabled by ‘drqien’ (IFCTRL; see Table 57), this
bit is asserted after every load of the packet size store into DBCH/DBCL during an ‘a(chǎn)utodrq’
DMA sequence. ‘drqi’ is cleared along with its associated interrupt by the microcontroller
writing logic 1 to ‘drqi’.
Ultra ATA stop before end of transfer interrupt: if enabled by ‘ultra_stopien’ (IFCTRL; see
Table 57), this bit is asserted if the host stops an ultra ATA data transfer before the
TRANSFER COUNTER has reached zero, when ‘a(chǎn)utodrq’ is selected, or before the
DBCH/DBCL task file registers reach zero when ‘a(chǎn)utodrq’ is not selected. ‘ultra_stop’ is
cleared along with its associated interrupt by the microcontroller writing logic 1 to
‘ultra_stop’ (IFSTAT; see Table 70).
Data transfer busy: this bit indicates if a data transfer is taking place. It is asserted by
writing to the DTRG register and is negated at the end of the transfer.
Interrupt/status transfer busy: in ATAPI mode this bit is asserted when the host writes to the
ATAPI device control register and sets the ‘srsti’ bit. It is negated when the microcontroller
reads the ADCTR register or by writing a logic 1 to the ‘srst’ (ADCTR; see Table 68).
It should be noted that if this bit is asserted in the ATAPI mode then the microcontroller
interrupt will also be asserted. The ‘srsti’ interrupt cannot be disabled.
The reset command 08 has been received: this bit indicates that the last command
received was the 08 reset command. Reading the command register ACMD will negate this
bit and its associated interrupt.
The A0 command auto sequence is completed or ultra ATA CRC error flag: this bit
indicates that A0 command auto sequence is completed i.e. the correct A0 command has
been read and the host interface has been configured to receive the 12 byte packet. This
bit does generate an interrupt but should be used in conjunction with the ‘dtei’ interrupt.
A microcontroller write to DTACK will negate the ‘a(chǎn)0comp’ bit.
6
dtei
5
drqi
4
ultra_stop
3
dtbsy
2
srsti
1
reset08
0
a0comp/
crc_error
After an ultra DMA data transfer (read from the SAA7381 or write to the SAA7381) this bit
may be used in conjunction with the DTEI interrupt to indicate data integrity. If the
‘crc_error’ bit = 0 then the last data transfer was corrupt. Again writing to DTACK will
negate this bit.
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