
8
EPSON
S1C8F360 TECHNICAL MANUAL
3 CPU AND BUS CONFIGURATION
3 CPU AND BUS CONFIGURATION
In this section, we will explain the CPU, operating mode and bus configuration.
3.1 CPU
The S1C8F360 utilize the S1C88 8-bit core CPU
whose resistor configuration, command set, etc. are
virtually identical to other units in the family of
processors incorporating the S1C88.
See the "S1C88 Core CPU Manual" for the S1C88.
Specifically, the S1C8F360 employ the Model 3
S1C88 CPU which has a maximum address space of
512K bytes
× 4.
3.2 Internal Memory
The S1C8F360 is equipped with internal PROM
(Flash EEPROM) and RAM as shown in Figure
3.2.1. Small scale applications can be handled by
one chip. It is also possible to utilize internal
memory in combination with external memory.
Furthermore, internal PROM can be disconnected
from the bus and the resulting space released for
external applications.
3.2.2 RAM
The internal RAM capacity is 2K bytes and is
allocated to 00F000H–00F7FFH.
Even when external memory which overlaps the
internal RAM area is expanded, the RAM area is
not released to external memory. Access to this area
is via internal RAM.
3.2.3 I/O memory
A memory mapped I/O method is employed in the
S1C8F360 for interfacing with internal peripheral
circuit. Peripheral circuit control bits and data
register are arranged in data memory space.
Control and data exchange are conducted via
normal memory access. I/O memory is arranged in
page 0: 00FF00H–00FFFFH area.
See Section 5.1, "I/O Memory Map", for details of
the I/O memory.
Even when external memory which overlaps the I/O
memory area is expanded, the I/O memory area is
not released to external memory. Access to this area
is via I/O memory.
3.2.4 Display memory
The S1C8F360 is equipped with an internal display
memory which stores a display data for LCD
driver.
Display memory is arranged in page 0: 00Fx00H–
00Fx42H (x = 8–DH) in the data memory area. See
Section 5.12, "LCD Controller", for details of the
display memory. Like the I/O memory, display
memory cannot be released to external memory.
3.3 Exception Processing Vectors
000000H–000025H in the program area of the
S1C8F360 is assigned as exception processing
vectors. Furthermore, from 000028H to 0000FFH,
software interrupt vectors are assignable to any two
bytes which begin with an even address.
Table 3.3.1 lists the vector addresses and the
exception processing factors to which they corre-
spond.
Fig. 3.2.1 Internal memory map
3.2.1 PROM
The S1C8F360 has a built-in 60K-byte Flash
EPROM. The PROM is allocated to 000000H–
00EFFFH.
The PROM areas shown above can be released to
external memory depending on the setting of the
_______
MCU/MPU terminal. (See "3.5 Chip Mode".)
00FFFFH
00FF00H
00FD42H
00F800H
00F7FFH
00F000H
00EFFFH
000000H
I/O memory
Display memory
RAM (2K bytes)
PROM
(60K bytes)