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參數(shù)資料
| 型號(hào)： | S1C8F360F |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, FLASH, 8.2 MHz, MICROCONTROLLER, PQFP176 |
| 封裝： | QFP18-176 |
| 文件頁數(shù)： | 133/217頁 |
| 文件大小： | 1753K |
| 代理商： | S1C8F360F |
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12
EPSON
S1C8F360 TECHNICAL MANUAL
3 CPU AND BUS CONFIGURATION
3.6 External Bus
The S1C8F360 has bus terminals that can address a
maximum of 512K
× 4 bytes and memory (and
other) devices can be externally expanded accord-
ing to the range of each bus mode described in the
previous section.
3.6.2 Address bus
The S1C8F360 possesses a 19-bit external address
bus A0–A18. The terminals and output circuits of
address bus A0–A18 are shared with output ports
R00–R07 (=A0–A7), R10–R17 (=A8–A15) and R20–
R22 (=A16–A18), switching between these functions
being determined by the bus mode setting.
In the single chip mode, the 19-bit terminals are all
set as output ports R00–R07, R10–R17 and R20–R22.
In the expanded 64K mode, 16 of the 19-bit termi-
nals, A0–A15, are set as the address bus, while the
remaining 3 bits, A16–A18, are set as output ports
R20–R22.
In the expanded 512K minimum and maximum
modes, all of the 19-bit terminals are set as the
address bus (A0–A18).
When set as an address bus, the data register and
high impedance control register of each output port
are detached from the output circuit and used as a
general purpose data register with read/write
capabilities.
S1C8F360
External
device
External
device
External
device
External
device
Address bus (A0–A18)
Data bus (D0–D7)
RD
WR
CE0
CE1
CE2
CE3
BREQ
BACK
Fig. 3.6.1 External bus lines
Below is an explanation of external bus terminals.
For information on control methods, see Section 5.2,
"System Controller and Bus Control".
3.6.1 Data bus
The S1C8F360 possesses an 8-bit external data bus
(D0–D7). The terminals and I/O circuits of data bus
D0–D7 are shared with I/O ports P00–P07, switch-
ing between these functions being determined by
the bus mode setting.
In the single chip mode, the 8-bit terminals are all
set as I/O ports P00–P07 and in the other expanded
modes, they are set as data bus (D0–D7).
When set as data bus, the data register and I/O
control register of each I/O port are detached from
the I/O circuits and usable as a general purpose
data register with read/write capabilities.
Each data bus line has a built-in pull-up resistor
that goes ON in input mode. (The same holds true
when the terminals are used as I/O ports.)
I/O
port
Data
bus
P00
P01
P02
P03
P04
P05
P06
P07
D0
D1
D2
D3
D4
D5
D6
D7
64K
Bus mode
512K
(max.)
512K
(min.)
Bus mode
Single
chip
Fig. 3.6.1.1 Correspondence between data bus
and I/O ports
Fig. 3.6.2.1 Correspondence between address bus
and output ports
______
_______
3.6.3 Read (RD)/write (WR) signals
The output terminals and output circuits for the
_____
read (RD)/write (WR) signals directed to external
devices are shared respectively with output ports
R23 and R24, switching between these functions
being determined by the bus mode setting.
In the single chip mode, both of these terminals are
set as output port terminals and in the other
_____
expanded modes, they are set as read (RD)/write
_____
(WR) signal output terminals. When set as read
_____
(RD)/write (WR) signal output terminal, the data
register and high impedance control register for
each output port (R23, R24) are detached from the
output circuit and is usable as a general purpose
data register with read/write capabilities.
Output
port
Address
bus
R00
R01
R02
R03
R04
R05
R06
R07
R10
R11
R12
R13
R14
R15
R16
R17
R20
R21
R22
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
A16
A17
A18
64K
Bus mode
512K
(max.)
512K
(min.)
64K
Bus mode
Single
chip
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| S1C8F360F413100 | 功能描述:16位微控制器 - MCU 8-bit Flash 60KB LCD Dr. 51 x 32 RoHS:否 制造商:Texas Instruments 核心:RISC 處理器系列:MSP430FR572x 數(shù)據(jù)總線寬度:16 bit 最大時(shí)鐘頻率:24 MHz 程序存儲(chǔ)器大小:8 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:2 V to 3.6 V 工作溫度范圍:- 40 C to + 85 C 封裝 / 箱體:VQFN-40 安裝風(fēng)格:SMD/SMT |
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