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參數(shù)資料
| 型號(hào)： | S1C8F360F |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, FLASH, 8.2 MHz, MICROCONTROLLER, PQFP176 |
| 封裝： | QFP18-176 |
| 文件頁(yè)數(shù)： | 180/217頁(yè) |
| 文件大?。?/td> | 1753K |
| 代理商： | S1C8F360F |
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S1C8F360 TECHNICAL MANUAL
EPSON
55
5 PERIPHERAL CIRCUITS AND THEIR OPERATION (Output Ports)
s FOUT output (R34)
In order for the S1C8F360 to provide clock signal to
an external device, a FOUT signal (divided clock of
oscillation clock fOSC1 or fOSC3) can be output from
the output port terminal R34.
Figure 5.6.5.11 shows the configuration of output
port R34.
Register R34D
Register FOUTON
R34 output
FOUT signal
Fig. 5.6.5.11 Configuration of R34
The output control for the FOUT signal is done by
the register FOUTON. When you set "1" for the
FOUTON, the FOUT signal is output from the
output port terminal R34, when "0" is set, the HIGH
(VDD) level is output. At this time, "1" must always
be set for the data register R34D.
The frequency of the FOUT signal can be selected in
software by setting the registers FOUT0–FOUT2.
The frequency is selected any one from among
eight settings as shown in Table 5.6.5.4.
Table 5.6.5.4 FOUT frequency setting
FOUT2
FOUT frequency
0
1
fOSC1 / 1
fOSC1 / 2
fOSC1 / 4
fOSC1 / 8
fOSC3 / 1
fOSC3 / 2
fOSC3 / 4
fOSC3 / 8
FOUT1
0
1
0
1
FOUT0
0
1
0
1
0
1
0
1
fOSC1:
fOSC3:
OSC1 oscillation frequency
OSC3 oscillation frequency
When the FOUT frequency is made "fOSC3/n", you
must turn on the OSC3 oscillation circuit before
outputting FOUT. A time interval of several 100
sec to several 10 msec, from the turning ON of the
OSC3 oscillation circuit to until the oscillation
stabilizes, is necessary, due to the oscillation
element that is used. Consequently, if an abnormal-
ity occurs as the result of an unstable FOUT signal
being output externally, you should allow an
adequate waiting time after turning ON of the
OSC3 oscillation, before turning outputting FOUT.
(The oscillation start time will vary somewhat
depending on the oscillator and on the externally
attached parts. Refer to the oscillation start time
example indicated in Chapter 10, "ELECTRICAL
CHARACTERISTICS".)
At initial reset, OSC3 oscillation circuit is set to OFF
state.
Since the FOUT signal is generated asynchronously
from the register FOUTON, when the signal is
turned ON or OFF by the register settings, a hazard
of a 1/2 cycle or less is generated.
Figure 5.6.5.12 shows the output waveform of the
FOUT signal.
FOUTON
FOUT output (R34)
01
Fig. 5.6.5.12 Output waveform of FOUT signal
s BZ output (R50), BZ output (R51)
In order for the S1C8F360 to drive an external
buzzer, a BZ signal (sound generator output) can be
output from the output port terminal R50. Further-
more, the R51 output port terminal can be used to
output a BZ signal (BZ inverted signal).
The configuration of the output ports R50 and R51
is shown in Figure 5.6.5.13.
BZ signal
R
SQ
One-shot
time up
R50 output
Register BZSTP
Register BZON
Register BZSHT
Register R50D
R51 output
Mask option
Register R51D
Fig. 5.6.5.13 Configuration of R50 and R51
The output control for the BZ (BZ) signal is done by
the registers BZON, BZSHT and BZSTP. When you
set "1" for the BZON or BZSHT, the BZ (BZ) signal
is output from the output port terminal R50 (R51).
When "0" is set for the BZON or "1" is set for the
BZSTP, the R50 goes LOW (VSS) and the R51 goes
HIGH (VDD).
To output the BZ signal, "0" must always be set for
the data register R50D. The data register R51D does
not affect the BZ output.
The BZ (BZ) signal is generated by the sound
generator. With respect to control of frequency and
envelope, see "5.13 Sound Generator".
Since the BZ (BZ) signal is generated asynchro-
nously from the registers BZON, BZSHT and
BZSTP, when the signal is turned ON or OFF by
setting the registers, a hazard of a 1/2 cycle or less
is generated.
Figure 5.6.5.14 shows the output waveform of the
BZ (BZ) signal.
BZON/BZSHT
BZ output (R50)
BZ output (R51) *
01
when selected by mask option
Fig. 5.6.5.14 BZ (BZ) output waveform
相關(guān)PDF資料 |
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| S1D13305F00B | 640 X 256 PIXELS CRT CHAR OR GRPH DSPL CTLR, PQFP60 |
| S1D13305F00A | 640 X 256 PIXELS CRT CHAR OR GRPH DSPL CTLR, PQFP60 |
| S1D13600F00A | CRT OR FLAT PNL GRPH DSPL CTLR, PQFP64 |
| S1D13700F02A100 | 320 X 240 PIXELS CRT OR FLAT PNL GRPH DSPL CTLR, PQFP64 |
| S1D13706F00A | 320 X 240 PIXELS CRT OR FLAT PNL GRPH DSPL CTLR, PQFP100 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| S1C8F360F413100 | 功能描述:16位微控制器 - MCU 8-bit Flash 60KB LCD Dr. 51 x 32 RoHS:否 制造商:Texas Instruments 核心:RISC 處理器系列:MSP430FR572x 數(shù)據(jù)總線寬度:16 bit 最大時(shí)鐘頻率:24 MHz 程序存儲(chǔ)器大小:8 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:2 V to 3.6 V 工作溫度范圍:- 40 C to + 85 C 封裝 / 箱體:VQFN-40 安裝風(fēng)格:SMD/SMT |
| S1C8F360F513200 | 功能描述:16位微控制器 - MCU 8-bit Flash 60KB LCD Dr. 51 x 32 RoHS:否 制造商:Texas Instruments 核心:RISC 處理器系列:MSP430FR572x 數(shù)據(jù)總線寬度:16 bit 最大時(shí)鐘頻率:24 MHz 程序存儲(chǔ)器大小:8 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:2 V to 3.6 V 工作溫度范圍:- 40 C to + 85 C 封裝 / 箱體:VQFN-40 安裝風(fēng)格:SMD/SMT |
| S1C8F626 | 制造商:EPSON 制造商全稱:EPSON 功能描述:8-bit Single Chip Microcomputer |
| S1C-8-S | 制造商:GRIPCO 功能描述: |
| S1CFB | 制造商:Hubbell Wiring Device-Kellems 功能描述:FLOORBOX, SYSTEM ONE, CAST IRON |
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