參數(shù)資料
型號(hào): S1C8F360F
元件分類: 微控制器/微處理器
英文描述: 8-BIT, FLASH, 8.2 MHz, MICROCONTROLLER, PQFP176
封裝: QFP18-176
文件頁(yè)數(shù): 160/217頁(yè)
文件大小: 1753K
代理商: S1C8F360F
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S1C8F360 TECHNICAL MANUAL
EPSON
37
5 PERIPHERAL CIRCUITS AND THEIR OPERATION (System Controller and Bus Control)
CE0–CE3: 00FF00HD0–D3
Sets the CE output terminals being used.
When "1" is written: CE output enable
When "0" is written: CE output disable
Reading:
Valid
CE output is enabled when a "1" is written to
registers CE0–CE3 which correspond to the CE
output being used. A "0" written to any of the
registers disables CE signal output from that
terminal and it reverts to its alternate function as an
output port terminal (R30–R33).
At initial reset, register CE0 is set to "0" in the MCU
mode and in the MPU mode, "1" is set in the
register. Registers CE1–CE3 are always set to "0"
regardless of the MCU/MPU mode setting.
Note: To avoid a malfunction from an interrupt
generated before the bus configuration is
initialized, all interrupts including NMI are
masked until you write an optional value into
address "00FF00H".
SPP0–SPP7: 00FF01H
Sets the page address of stack area. In single chip
mode and expanded 64K mode, set page address to
"00H".
In expanded 512K mode, it can be set to any value
within the range "00H"–"27H".
Since a carry and borrow from/to the stack pointer
SP is not reflected in register SPP, the upper limit
on continuous use of the stack area is 64K bytes.
At initial reset, this register is set to "00H" (page 0).
Note: To avoid a malfunction from an interrupt
generated before the bus configuration is
initialized, all interrupts including NMI are
disabled, until you write an optional value
into "00FF01H" address. Furthermore, to
avoid generating an interrupt while the stack
area is being set, all interrupts including NMI
are disabled in one instruction execution
period after writing to address "00FF01H".
BSMD0, BSMD1: 00FF00HD6, D7
Bus modes are set as shown in Table 5.2.6.2.
Table 5.2.6.2 Bus mode settings
BSMD1
Bus mode
1
0
Expanded 512K maximum mode
Expanded 512K minimum mode
Expanded 64K mode (MPU mode)
Single chip mode (MCU mode)
Expanded 64K mode (MPU mode)
BSMD0
1
0
1
0
Setting values
The single chip mode setting is only possible when
this IC is used in the MCU mode. The single chip
mode setting is incompatible with the MPU mode,
since this mode does not utilize internal PROM.
At initial reset, single chip mode is set in the MCU
mode and expanded 64K mode is set in the MPU
mode.
CEMD0, CEMD1: 00FF00HD4, D5
Sets the CE signal address range (valid only in the
expanded 64K mode
).
Settings are made according to external memory
chip size as shown in Table 5.2.6.3.
Table 5.2.6.3 CE signal settings
CEMD1
Usable terminals
1
0
CE0
CE0, CE1
CE0–CE3
CEMD0
1
0
1
0
Address range
64K bytes
32K bytes
16K bytes
8K bytes
These settings are invalid for any mode other than
expanded 64K mode.
At initial reset, each register is set to "1" (64K bytes).
Settings of these registers are valid only in the
MPU mode. CEMD0 and CEMD1 can be used as
general purpose registers with read/write
capabilities in the MCU mode.
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