參數(shù)資料
型號(hào): S1C8F360F
元件分類(lèi): 微控制器/微處理器
英文描述: 8-BIT, FLASH, 8.2 MHz, MICROCONTROLLER, PQFP176
封裝: QFP18-176
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文件大?。?/td> 1753K
代理商: S1C8F360F
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128
EPSON
S1C8F360 TECHNICAL MANUAL
5 PERIPHERAL CIRCUITS AND THEIR OPERATION (A/D Converter)
5.15.4 A/D conversion
s Setting the A/D input terminal
When using the A/D converter, it is necessary to
set up the terminals used for analog input from the
P14–P17 initialized as the I/O port terminals. Four
terminals can all be used as analog input terminals.
The PAD (PAD4–PAD7) register is used to set
analog input terminals. When the PAD register bits
are set to "1", the corresponding terminals function
as the analog input terminals.
Table 5.15.4.1 Correspondence between A/D input
terminal and PAD register
Terminal
P14 (AD4)
P15 (AD5)
P16 (AD6)
P17 (AD7)
A/D input control register
PAD4
PAD5
PAD6
PAD7
s Setting the input clock
The A/D conversion clock can be selected from
eight types shown in Table 5.15.4.2. The selection is
done using the PSAD register.
Table 5.15.4.2 Input clock selection
Division
ratio
fOSC1/1
fOSC3/64
fOSC3/32
fOSC3/16
fOSC3/8
fOSC3/4
fOSC3/2
fOSC3/1
Output
control
PRAD
register
"1": ON
"0": OFF
PSAD2
1
0
Selection register
PSAD1
1
0
1
0
PSAD0
1
0
1
0
1
0
1
0
The selected clock is input to the A/D converter by
writing "1" to the PRAD register.
Note: When the OSC3 oscillation circuit is made
the clock source, it is necessary to turn the
OSC3 oscillation ON, prior to using the
A/D converter.
From the time the OSC3 oscillation circuit
is turning ON until oscillation stabilizes, an
interval of several msec to several 10
msec is necessary. Consequently, you
should allow an adequate waiting time
after turning the OSC3 oscillation circuit
ON before starting the count of the
programmable timer. (The oscillation start
time will vary somewhat depending on the
oscillator and on external parts. Refer to
the oscillation start time example indicated
in Chapter 10, "ELECTRICAL CHARAC-
TERISTICS".)
At initial reset, OSC3 oscillation circuit is
set to OFF status.
The clock division ratio (see Table
5.15.4.2) must be set so that the A/D
conversion clock frequency is 1 MHz or
less. Furthermore, the A/D conversion
clock frequency should be changed
according to the voltage to be used. Refer
to Chapter 10, "ELECTRICAL CHARAC-
TERISTICS".
The input clock should be set when the
A/D converter stops. Changing in the A/D
converter operation may cause a malfunc-
tion.
To prevent malfunction, do not start A/D
conversion (writing to the CHS register)
when the A/D conversion clock is not
being output from the prescaler, and do
not turn the prescaler output clock off
during A/D conversion.
s Selecting the input signal
The analog signals from the AD4 (P14)–AD7 (P17)
terminals are input to the multiplexer, and the
analog input channel for A/D conversion is
selected by software. This selection can be done
using the CHS register as shown in Table 5.15.4.3.
Table 5.15.4.3 Selection of analog input channel
Input channel
AD7
AD6
AD5
AD4
CHS1
1
0
CHS0
1
0
1
0
s A/D conversion operation
An A/D conversion starts by writing data to the
ADRUN register. For example, when performing
A/D conversion using AD7 as the analog input,
write "1" (1, 1) to the CHS register (CHS1, CHS0)
and then write "1" to the ADRUN register. The A/D
input channel is selected and the A/D conversion
starts. However, it is necessary that the P17 termi-
nal has been set as an analog input terminal.
The built-in sample & hold circuit starts sampling
of the analog input specified from tAD after writing.
When the sampling is completed, the held analog
input voltage is converted into a 10-bit digital value
in successive-approximation architecture.
The conversion result is loaded into the ADDR
(ADDR0–ADDR9) register. ADDR0 is the LSB and
ADDR9 is the MSB.
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