
S1C8F360 TECHNICAL MANUAL
EPSON
i
CONTENTS
Preface
The S1C8F360 is a development tool/preprocessor IC for the S1C88862, S1C88861, S1C88832, S1C88348,
S1C88317 and S1C88316. The ROM has been changed to a Flash EEPROM (described as PROM in this
manual) and a 10-bit A/D converter with four analog inputs is included. Almost all other circuits are
compatible with the S1C883xx/888xx mask ROM models.
Furthermore, an exclusive PROM writer should be used for PROM programming. Refer to Appendix,
"PROM Programming", for how to program the PROM.
Refer to the following manuals in addition to this manual. (Note that the pin assignment of the S1C8F360 is
different from that of the S1C883xx/888xx.)
S1C88348/317/316/308 Technical Manual
S1C88832/88862 Technical Manual
Contents
1
INTRODUCTION .............................................................................................. 1
1.1
Features ............................................................................................................................. 1
1.2
Block Diagram ................................................................................................................... 2
1.3
Pin Layout Diagram .......................................................................................................... 3
1.4
Pin Description .................................................................................................................. 4
1.5
Mask Option ....................................................................................................................... 5
2
POWER SUPPLY ............................................................................................... 6
2.1
Operating Voltage .............................................................................................................. 6
2.2
Internal Power Supply Circuit ........................................................................................... 6
2.3
Heavy Load Protection Mode ............................................................................................ 7
3
CPU AND BUS CONFIGURATION ................................................................ 8
3.1
CPU ...................................................................................................................................8
3.2
Internal Memory ................................................................................................................ 8
3.2.1 PROM ....................................................................................................................................... 8
3.2.2 RAM .......................................................................................................................................... 8
3.2.3 I/O memory ............................................................................................................................... 8
3.2.4 Display memory ........................................................................................................................ 8
3.3
Exception Processing Vectors ........................................................................................... 8
3.4
CC (Customized Condition Flag) ...................................................................................... 9
3.5
Chip Mode .......................................................................................................................... 9
3.5.1 MCU mode and MPU mode .....................................................................................................9
3.5.2 Bus mode ................................................................................................................................. 10
3.6
External Bus ......................................................................................................................12
3.6.1 Data bus .................................................................................................................................. 12
3.6.2 Address bus ............................................................................................................................. 12
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3.6.3 Read (RD)/write (WR) signals ................................................................................................. 12
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3.6.4 Chip enable (CE) signal .......................................................................................................... 13
3.6.5 WAIT control ........................................................................................................................... 14
3.6.6 Bus authority release state ...................................................................................................... 15
4
INITIAL RESET ............................................................................................... 16
4.1
Initial Reset Factor ........................................................................................................... 16
4.2
Initial Settings After Initial Reset ...................................................................................... 17