參數(shù)資料
型號(hào): S1C8F360F
元件分類: 微控制器/微處理器
英文描述: 8-BIT, FLASH, 8.2 MHz, MICROCONTROLLER, PQFP176
封裝: QFP18-176
文件頁(yè)數(shù): 178/217頁(yè)
文件大小: 1753K
代理商: S1C8F360F
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S1C8F360 TECHNICAL MANUAL
EPSON
53
5 PERIPHERAL CIRCUITS AND THEIR OPERATION (Output Ports)
Table 5.6.5.2 Frequencies of CL and FR signals
Drive duty
1/32
1/16
1/8
FR signal (Hz)
32
64
CL signal (Hz)
2,048
1,024
Since the signals are generated asynchronously
from the registers LCCLK and LCFRM, when the
signals are turned ON or OFF by the register
settings, a hazard of a 1/2 cycle or less is generated.
Figure 5.6.5.2 shows the output waveforms of the
CL and FR signals.
Fig. 5.6.5.2 Output waveforms of CL and FR signals
(when 1/6 duty is selected)
s TOUT output (R27)
In order for the S1C8F360 to provide clock signal to
an external device, the output port terminal R27 can
be used to output a TOUT signal (clock output by
the programmable timer). The configuration of
output port R27 is shown in Figure 5.6.5.3.
Register R27D
Register PTOUT
R27 output
TOUT signal
Fig. 5.6.5.3 Configuration of R27
The output control for the TOUT signal is done by
the register PTOUT. When you set "1" for the
PTOUT, the TOUT signal is output from the output
port terminal R27, when "0" is set, the HIGH (VDD)
level is output. At this time, "1" must always be set
for the data register R27D.
The TOUT signal is the programmable timer
underflow divided by 1/2.
With respect to frequency control, see "5.11 Pro-
grammable Timer".
Since the TOUT signal is generated asynchronously
from the register PTOUT, when the signal is turned
ON or OFF by the register settings, a hazard of a 1/
2 cycle or less is generated.
Figure 5.6.5.4 shows the output waveform of the
TOUT signal.
PTOUT
TOUT output (R27)
01
Fig. 5.6.5.4 Output waveform of TOUT signal
LCCLK/LCFRM
CL output (R25)
FR output (R26)
01
s FOUT output (R34)
In order for the S1C8F360 to provide clock signal to
an external device, a FOUT signal (oscillation clock
fOSC1 or fOSC3 dividing clock) can be output from
the output port terminal R34.
Figure 5.6.5.5 shows the configuration of output
port R34.
Register R34D
Register FOUTON
R34 output
FOUT signal
Fig. 5.6.5.5 Configuration of R34
The output control for the FOUT signal is done by
the register FOUTON. When you set "1" for the
FOUTON, the FOUT signal is output from the
output port terminal R34, when "0" is set, the HIGH
(VDD) level is output. At this time, "1" must always
be set for the data register R34D.
The frequency of the FOUT signal can be selected in
software by setting the registers FOUT0–FOUT2.
The frequency is selected any one from among
eight settings as shown in Table 5.6.5.3.
Table 5.6.5.3 FOUT frequency setting
FOUT2
FOUT frequency
0
1
fOSC1 / 1
fOSC1 / 2
fOSC1 / 4
fOSC1 / 8
fOSC3 / 1
fOSC3 / 2
fOSC3 / 4
fOSC3 / 8
FOUT1
0
1
0
1
FOUT0
0
1
0
1
0
1
0
1
fOSC1:
fOSC3:
OSC1 oscillation frequency
OSC3 oscillation frequency
When the FOUT frequency is made "fOSC3/n", you
must turn on the OSC3 oscillation circuit before
outputting FOUT. A time interval of several msec to
several 10 msec, from the turning ON of the OSC3
oscillation circuit to until the oscillation stabilizes, is
necessary, due to the oscillation element that is used.
Consequently, if an abnormality occurs as the result
of an unstable FOUT signal being output externally,
you should allow an adequate waiting time after
turning ON of the OSC3 oscillation, before turning
outputting FOUT. (The oscillation start time will
vary somewhat depending on the oscillator and on
the externally attached parts. Refer to the oscillation
start time example indicated in Chapter 10, "ELEC-
TRICAL CHARACTERISTICS".)
At initial reset, OSC3 oscillation circuit is set to OFF
state.
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