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參數(shù)資料
| 型號(hào)： | S1C6P466D0A0A00 |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | MICROCONTROLLER, UUC140 |
| 封裝： | DIE-140 |
| 文件頁(yè)數(shù)： | 85/174頁(yè) |
| 文件大?。?/td> | 1582K |
| 代理商： | S1C6P466D0A0A00 |
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8
EPSON
S1C6P466 TECHNICAL MANUAL
CHAPTER 2: POWER SUPPLY AND INITIAL RESET
2.2 Initial Reset
To initialize the S1C6P466 circuits, initial reset must be executed. The S1C6P466 supports the initial reset
factor below.
External initial reset by the RESET terminal
When the power is turned on, be sure to initialize using the reset function. It is not guaranteed that the
circuits are initialized by only turning the power on.
Figure 2.2.1 shows the configuration of the initial reset circuit.
RESET
OSC2
OSC1
RQ
S
Internal
initial
reset
Divider
VDD
1 Hz
2 Hz
OSC1
oscillation
circuit
Noise
reject
circuit
Fig. 2.2.1 Configuration of initial reset circuit
2.2.1 Reset terminal (RESET)
Initial reset can be executed externally by setting the reset terminal to a low level (VSS). After that the
initial reset is released by setting the reset terminal to a high level (VDD) and the CPU starts operation.
The reset input signal is maintained by the RS latch and becomes the internal initial reset signal. The RS
latch is designed to be released by a 2 Hz signal (high) that is divided by the OSC1 clock. Therefore in
normal operation, a maximum of 250 msec (when fOSC1 = 32.768 kHz) is needed until the internal initial
reset is released after the reset terminal goes to high level. Be sure to maintain a reset input of 0.1 msec or
more.
However, when turning the power on, the reset terminal should be set at a low level as in the timing
shown in Figure 2.2.1.1.
VDD
RESET
2.0 msec or more
2.7 V
0.5VDD
0.1VDD or less (low level)
Power on
Fig. 2.2.1.1 Initial reset at power on
The reset terminal should be set to 0.1VDD or less (low level) until the supply voltage becomes 2.7 V or
more. After that, a level of 0.5VDD or less should be maintained more than 2.0 msec.
In the S1C6P466, a low level input to the reset terminal initializes some analog circuits as well as the
internal logic. At this time, 10 A or more current is consumed as the bias current.
2.2.2 Internal register at initial resetting
Initial reset initializes the CPU as shown in Table 2.2.2.1.
The registers and flags which are not initialized by initial reset should be initialized in the program if
necessary.
In particular, the stack pointers SP1 and SP2 must be set as a pair because all the interrupts including
NMI are masked after initial reset until both the SP1 and SP2 stack pointers are set with software.
When data is written to the EXT register, the E flag is set and the following instruction will be executed in
the extended addressing mode.
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