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參數(shù)資料
| 型號(hào)： | S1C6P466D0A0A00 |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | MICROCONTROLLER, UUC140 |
| 封裝： | DIE-140 |
| 文件頁(yè)數(shù)： | 101/174頁(yè) |
| 文件大?。?/td> | 1582K |
| 代理商： | S1C6P466D0A0A00 |
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22
EPSON
S1C6P466 TECHNICAL MANUAL
CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Oscillation Circuit)
As shown in Figure 4.3.3.1, the ceramic oscillation circuit can be configured by connecting the ceramic
oscillator (Max. 4 MHz) between the OSC3 and OSC4 terminals, capacitor CGC between the OSC3 and
OSC4 terminals, and capacitor CDC between the OSC4 and VSS terminals. For both CGC and CDC, connect
capacitors that are about 30 pF. To reduce current consumption of the OSC3 oscillation circuit, oscillation
can be stopped by the software (OSCC register).
When the OSC3 oscillation circuit is not used, leave the OSC3 and OSC4 terminals open.
4.3.4 Operating voltage
The S1C6P466 generates the VD1 voltage internally for the OSC1 oscillation circuit in order to stabilize
oscillation. In the S1C6P466, the VD1 voltage is used only for the OSC1 oscillation circuit and the voltage
level is fixed at 1.85
±0.3 V.
Therefore, setting of the VDC register (FF00HD0) required in the mask ROM model is invalidated and
does not affect the VD1 voltage level. However, note that the VDC register value affects the CPU clock
switch control.
When using the S1C6P466 as a development tool for the S1C63454/63458/63466, switch the operating
voltage using the VDC register according to the control sequence of the model (refer to the "Technical
Manual").
Furthermore, internal logic circuits of the S1C6P466 except for the OSC1 oscillation circuit operate with
the source voltage supplied between the VDD and VSS terminal.
4.3.5 Switching operating clock
The CPU system clock is switched to OSC1 or OSC3 by software (CLKCHG register).
When using OSC3 as the CPU system clock, first turn the OSC3 oscillation ON and then switch the clock
after waiting 5 msec or more for oscillation stabilization.
When switching from OSC3 to OSC1, turn the OSC3 oscillation circuit OFF after switching the clock.
OSC1
→ OSC3
OSC3
→ OSC1
1. Set OSCC to "1" (OSC3 oscillation ON).
1. Set CLKCHG to "0" (OSC3
→ OSC1).
2. Maintain 5 msec or more.
2. Set OSCC to "0" (OSC3 oscillation OFF).
3. Set CLKCHG to "1" (OSC1
→ OSC3).
4.3.6 Clock frequency and instruction execution time
Table 4.3.6.1 shows the instruction execution time according to each frequency of the system clock.
Table 4.3.6.1 Clock frequency and instruction execution time
Clock frequency
OSC1: 32.768 kHz
OSC3: 4 MHz
Instruction execution time (
sec)
1-cycle instruction
2-cycle instruction
3-cycle instruction
61
122
183
0.5
1
1.5
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