參數(shù)資料
型號： S1C6P466D0A0A00
元件分類： 微控制器/微處理器
英文描述： MICROCONTROLLER, UUC140
封裝： DIE-140
文件頁數(shù)： 161/174頁
文件大小： 1582K
代理商： S1C6P466D0A0A00
S1C6P466 TECHNICAL MANUAL
EPSON
77
CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Serial Interface)
SCTRG: Clock trigger/status (FF70HD1)
This is a trigger to start input/output of synchronous clock (SCLK).
When writing
When "1" is written: Trigger
When "0" is written: No operation
When this trigger is supplied to the serial interface activating circuit, the synchronous clock (SCLK)
input/output is started.
As a trigger condition, it is required that data writing or reading on data registers SD0–SD7 be performed
prior to writing "1" to SCTRG. (The internal circuit of the serial interface is initiated through data writ-
ing/reading on data registers SD0–SD7.) In addition, be sure to enable the serial interface with the ESIF
register before setting the trigger.
Supply trigger only once every time the serial interface is placed in the RUN state. Refrain from perform-
ing trigger input multiple times, as leads to malfunctioning.
Moreover, when the synchronous clock SCLK is external clock, start to input the external clock after the
trigger.
When reading
When "1" is read: RUN (during input/output the synchronous clock)
When "0" is read: STOP (the synchronous clock stops)
When this bit is read, it indicates the status of serial interface clock.
After "1" is written to SCTRG, this value is latched till serial interface clock stops (8 clock counts). There-
fore, if "1" is read, it indicates that the synchronous clock is in input/output operation.
When the synchronous clock input/output is completed, this latch is reset to "0".
At initial reset, this bit is set to "0".
SD0–SD3, SD4–SD7: Serial interface data register (FF72H, FF73H)
These registers are used for writing and reading serial data.
When writing
When "1" is written: High level
When "0" is written: Low level
Write data to be output in these registers. The register data is converted into serial data and output from
the SOUT (P11) terminal; data bits set at "1" are output as high (VDD) level and data bits set at "0" are
output as low (VSS) level.
When reading
When "1" is read: High level
When "0" is read: Low level
The serial data input from the SIN (P10) terminal can be read from these registers.
The serial data input from the SIN (P10) terminal is converted into parallel data, as a high (VDD) level bit
into "1" and as a low (VSS) level bit into "0", and is loaded to these registers. Perform data reading only
while the serial interface is not running (i.e., the synchronous clock is neither being input or output).
At initial reset, these registers are undefined.
EISIF: Interrupt mask register (FFE3HD0)
Masking the interrupt of the serial interface can be selected with this register.
When "1" is written: Enabled
When "0" is written: Masked
Reading: Valid
With this register, it is possible to select whether the serial interface interrupt is to be masked or not.
At initial reset, this register is set to "0".
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