參數(shù)資料
型號： S1C6P466D0A0A00
元件分類： 微控制器/微處理器
英文描述： MICROCONTROLLER, UUC140
封裝： DIE-140
文件頁數(shù)： 160/174頁
文件大小： 1582K
代理商： S1C6P466D0A0A00
76
EPSON
S1C6P466 TECHNICAL MANUAL
CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Serial Interface)
PUL10: SIN (P10) pull-up control register (FF45HD0)
PUL12: SCLK (P12) pull-up control register (FF45HD2)
Sets the pull-up of the SIN terminal and the SCLK terminals (in the slave mode).
When "1" is written: Pull-up ON
When "0" is written: Pull-up OFF
Reading: Valid
Sets the pull-up resistor built into the SIN (P10) and SCLK (P12) terminals to ON or OFF.
SCLK pull-up is effective only in the slave mode. In the master mode, the PUL12 register can be used as a
general purpose register.
At initial reset, these registers are set to "1" and pull-up goes ON.
SCS1, SCS0: Clock mode selection register (FF71HD0, D1)
Selects the synchronous clock (SCLK) for the serial interface.
Table 4.11.5.2 Synchronous clock selection
SCS1
1
0
SCS0
1
0
1
0
Mode
Master mode
Slave mode
Synchronous clock
OSC1
OSC1 /2
Programmable timer
External clock
The maximum clock is limited to 1 MHz.
Synchronous clock (SCLK) is selected from among the above 4 types: 3 types of internal clock and
external clock.
When the programmable timer is selected, the signal that is generated by dividing the underflow signal
of the programmable timer (timer 1) in 1/2 is used as the synchronous clock. In this case, the program-
mable timer must be controlled before operating the serial interface. Refer to Section 4.10, "Programmable
Timer" for the control of the programmable timer.
At initial reset, external clock is selected.
SCPS: Clock phase selection register (FF71HD2)
Selects the timing for reading in the serial data input from the SIN (P10) terminal.
When "1" is written: Falling edge of SCLK
When "0" is written: Rising edge of SCLK
Reading: Valid
Select whether the fetching for the serial input data to registers (SD0–SD7) at the rising edge or falling
edge of the synchronous signal.
The input data fetch timing may be selected but output timing for output data is fixed at the falling edge
of SCLK.
At initial reset, this register is set to "0".
SDP: Data input/output permutation selection register (FF71HD3)
Selects the serial data input/output permutation.
When "1" is written: MSB first
When "0" is written: LSB first
Reading: Valid
Select whether the data input/output permutation will be MSB first or LSB first.
At initial reset, this register is set to "0".
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