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參數(shù)資料
| 型號(hào)： | S1C6P466D0A0A00 |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | MICROCONTROLLER, UUC140 |
| 封裝： | DIE-140 |
| 文件頁數(shù)： | 15/174頁 |
| 文件大?。?/td> | 1582K |
| 代理商： | S1C6P466D0A0A00 |
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S1C6P466 TECHNICAL MANUAL
EPSON
101
CHAPTER 6: DIFFERENCES FROM MASK ROM MODELS
6.2 Power Supply
Since the S1C6P466 is produced using the Flash EEPROM process, the characteristics are different from
those of the mask ROM models.
Operating voltage range
S1C6P466:
2.7 to 5.5 V
S1C63454:
2.2 to 5.5 V (Min. 1.8 V when the OSC3 is not used)
S1C63458:
2.2 to 5.5 V (Min. 1.8 V when the OSC3 is not used)
S1C63466:
2.2 to 5.5 V (Min. 1.8 V when the OSC3 is not used)
The circuit blocks of the S1C6P466 except for the OSC1 oscillation circuit and LCD driver (CPU,
PROM, RAM and peripheral digital circuits) operate with the source voltage supplied between the
VDD and VSS terminals. Therefore, the VDC register (FF00HD0) is invalidated and is used as a
general-purpose register. Writing "1" or "0" to this register does not affect the VD1 output voltage level.
Table 6.2.1 I/O memory FF00H (CPU operating voltage)
S1C6P466
S1C63454, S1C63458, S1C63466
Address
Comment
D3
D2
Register
D1
D0
Name
Init
1
0
FF00H
CLKCHG OSCC
0
VDC
R
R/W
CLKCHG
OSCC
0
VDC
0
–
0
OSC3
On
1
OSC1
Off
0
CPU clock switch
OSC3 oscillation On/Off
Unused
CPU operating voltage switch
Address
Comment
D3
D2
Register
D1
D0
Name
Init
1
0
FF00H
CLKCHG OSCC
0
VDC
R
R/W
CLKCHG
OSCC
0
VDC
0
–
0
OSC3
On
2.2 V
OSC1
Off
1.3 V
CPU clock switch
OSC3 oscillation On/Off
Unused
CPU operating voltage switch (1.3 V: OSC1, 2.2 V: OSC3)
Power supply terminal for the Flash EEPROM (VDDF)
The S1C6P466 has a power supply (+) terminal exclusively for use with the Flash EEPROM block
(VDDF). In Serial Programming mode or Normal Operation mode, the VDDF terminal should be
connected to the VDD terminal so that the VDD voltage level is supplied to the VDDF terminal.
Power supply terminal for the OSC1 oscillation circuit (VD1)
The VD1 voltage that is generated by the internal voltage regulator is used only for the OSC1 oscilla-
tion circuit to stabilize the oscillation. As explained above, the VDC register (FF00HD0) does not
affect the VD1 output voltage. In the S1C6P466, the VD1 voltage is fixed as follows:
VD1 output voltage = 1.85 V
± 0.3 V
Power supply for driving the LCD (VC1 to VC5)
The LCD system voltage circuit in the S1C6P466 generates the four voltages (for 1/4 bias): VC1, VC2,
VC4 and VC5. As similar to the S1C63454, S1C63458 and S1C63466, VC1 or VC2 is generated by the
internal voltage regulator and the other three voltages are generated by boosting and reducing it.
Table 6.2.2 lists the voltage values.
Table 6.2.2 LCD drive voltage
LCD drive voltage
VC1 (0.975 to 1.2 V)
VC2 (1.950 to 2.4 V)
VC4 (2.925 to 3.6 V)
VC5 (3.900 to 4.8 V)
VC1 (standard)
2
× VC1
3
× VC1
4
× VC1
1/2
× VC2
VC2 (standard)
3/2
× VC2
2
× VC2
VDD = 2.7 to 5.5V
Since the minimum operating voltage of the S1C6P466 is 2.7 V, either VC1 standard or VC2 standard
can be selected. VC2 standard can improve the display quality and reduce current consumption.
However, in the mask ROM model, VC1 standard must be selected when using the IC with a 2.6 V or
less operating voltage VDD. Take this into consideration when creating a program.
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