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參數(shù)資料
| 型號(hào)： | S1C6F567D0A0100 |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | MICROCONTROLLER, UUC141 |
| 封裝： | DIE-141 |
| 文件頁(yè)數(shù)： | 62/208頁(yè) |
| 文件大小： | 1561K |
| 代理商： | S1C6F567D0A0100 |
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146
EPSON
S1C6F567 TECHNICAL MANUAL
CHAPTER 7: SUMMARY OF NOTES
7.2 Summary of Notes by Function
Here, the cautionary notes are summed up by function category. Keep these notes well in mind when
programming.
Memory and stack
(1) Memory is not implemented in unused areas within the memory map. Further, some non-implemen-
tation areas and unused (access prohibition) areas exist in the display memory area and the peripheral
I/O area. If the program that accesses these areas is generated, its operation cannot be guaranteed.
Refer to Section 4.7.4, "Display memory", for the display memory, and the I/O memory maps shown
in Tables 4.1.1 (a)–(g) for the peripheral I/O area.
(2) Part of the RAM area is used as a stack area for subroutine call and register evacuation, so pay
attention not to overlap the data area and stack area.
(3) The S1C63000 core CPU handles the stack using the stack pointer for 4-bit data (SP2) and the stack
pointer for 16-bit data (SP1).
16-bit data are accessed in stack handling by SP1, therefore, this stack area should be allocated to the
area where 4-bit/16-bit access is possible (0100H to 01FFH). The stack pointers SP1 and SP2 change
cyclically within their respective range: the range of SP1 is 0000H to 03FFH and the range of SP2 is
0000H to 00FFH. Therefore, pay attention to the SP1 value because it may be set to 0200H or more
exceeding the 4-bit/16-bit accessible range in the S1C6F567 or it may be set to 00FFH or less. Memory
accesses except for stack operations by SP1 are 4-bit data access. After initial reset, all the interrupts
including NMI are masked until both the stack pointers SP1 and SP2 are set by software. Further, if
either SP1 or SP2 is re-set when both are set already, the interrupts including NMI are masked again
until the other is re-set. Therefore, the settings of SP1 and SP2 must be done as a pair.
Watchdog timer
(1) When the watchdog timer is being used, the software must reset it within 3-second cycles.
(2) Because the watchdog timer is set in operation state by initial reset, set the watchdog timer to disabled
state (not used) before generating an interrupt (NMI) if it is not used.
Oscillation circuit
(1) It takes at least 5 msec from the time the OSC3 oscillation circuit goes ON until the oscillation stabi-
lizes. Consequently, when switching the CPU operation clock from OSC1 to OSC3, do this after a
minimum of 5 msec have elapsed since the OSC3 oscillation went ON.
Further, the oscillation stabilization time varies depending on the external oscillator characteristics
and conditions of use, so allow ample margin when setting the wait time.
(2) When switching the clock form OSC3 to OSC1, use a separate instruction for switching the OSC3
oscillation OFF. An error in the CPU operation can result if this processing is performed at the same
time by the one instruction.
(3) The internal operating voltage of VD1 is fixed at 1.85±0.3 V. So it is not necessary to control the
operating voltage regardless of the operating clock selected.
Input port
(1) When input ports are changed from low to high by pull-up resistors, the rise of the waveform is
delayed on account of the time constant of the pull-up resistor and input gate capacitance. Hence,
when fetching input ports, set an appropriate waiting time. Particular care needs to be taken of the
key scan during key matrix configuration. Make this waiting time the amount of time or more calcu-
lated by the following expression.
10
× C × R
C: terminal capacitance 5 pF + parasitic capacitance ? pF
R: pull-up resistance 330 k
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