- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄98068 > S1C6F567D0A0100 MICROCONTROLLER, UUC141 PDF資料下載
參數(shù)資料
| 型號(hào)： | S1C6F567D0A0100 |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | MICROCONTROLLER, UUC141 |
| 封裝： | DIE-141 |
| 文件頁數(shù)： | 208/208頁 |
| 文件大?。?/td> | 1561K |
| 代理商： | S1C6F567D0A0100 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁第77頁第78頁第79頁第80頁第81頁第82頁第83頁第84頁第85頁第86頁第87頁第88頁第89頁第90頁第91頁第92頁第93頁第94頁第95頁第96頁第97頁第98頁第99頁第100頁第101頁第102頁第103頁第104頁第105頁第106頁第107頁第108頁第109頁第110頁第111頁第112頁第113頁第114頁第115頁第116頁第117頁第118頁第119頁第120頁第121頁第122頁第123頁第124頁第125頁第126頁第127頁第128頁第129頁第130頁第131頁第132頁第133頁第134頁第135頁第136頁第137頁第138頁第139頁第140頁第141頁第142頁第143頁第144頁第145頁第146頁第147頁第148頁第149頁第150頁第151頁第152頁第153頁第154頁第155頁第156頁第157頁第158頁第159頁第160頁第161頁第162頁第163頁第164頁第165頁第166頁第167頁第168頁第169頁第170頁第171頁第172頁第173頁第174頁第175頁第176頁第177頁第178頁第179頁第180頁第181頁第182頁第183頁第184頁第185頁第186頁第187頁第188頁第189頁第190頁第191頁第192頁第193頁第194頁第195頁第196頁第197頁第198頁第199頁第200頁第201頁第202頁第203頁第204頁第205頁第206頁第207頁當(dāng)前第208頁
S1C6F567 TECHNICAL MANUAL
EPSON
91
CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Serial Interface)
RXEN: Receive enable register (FF72HD2)
Sets the serial interface to the receive enabled status.
When "1" is written: Receive enabled
When "0" is written: Receive disabled
Reading: Valid
When "1" is written to RXEN, the serial interface shifts to the receive enabled status and shifts to the
receive disabled status when "0" is written.
Set RXEN to "0" when making the initial settings of the serial interface and similar operations.
At initial reset, this register is set to "0".
RXTRG: Receive trigger/status (FF72HD3)
Functions as the receive start trigger or preparation for the following data receiving and the operation
status indicator (during receiving/during stop).
When "1" is read: During receiving
When "0" is read: During stop
When "1" is written: Start receiving/following data receiving preparation
When "0" is written: Invalid
RXTRG has a slightly different operation in the clock synchronous system and the asynchronous system.
The RXTRG in the clock synchronous system is used as the trigger for starting receive operation.
Write "1" into RXTRG to start receiving at the point where the receive data has been read and the
following receive preparation has been done. (In the slave mode, SRDY becomes "0" at the point where
"1" has been written into into the RXTRG.)
In the asynchronous system, RXTRG is used for preparation of the following data receiving. Read the
received data located in the receive data buffer and write "1" into RXTRG to inform that the receive data
buffer has shifted to empty. When "1" has not been written to RXTRG, the overrun error flag OER is set to
"1" at the point where the following receiving has been completed. (When the receiving has been com-
pleted between the operation to read the received data and the operation to write "1" into RXTRG, an
overrun error occurs.)
In addition, RXTRG can be read as the status. In either clock synchronous mode or asynchronous mode,
when RXTRG is set to "1", it indicates receiving operation and when set to "0", it indicates that receiving
has stopped.
At initial reset, RXTRG is set to "0".
TRXD0–TRXD7: Transmit/receive data (FF74H, FF75H)
During transmitting
Transmitting data is set.
When "1" is written: High level
When "0" is written: Low level
Write the transmitting data prior to starting transmition.
In the case of continuous transmitting, wait for the transmit completion interrupt, then write the data.
The TRXD7 becomes invalid for the 7-bit asynchronous mode.
Converted serial data for which the bits set at "1" as High (VDD) level and for which the bits set at "0" as
Low (VSS) level are output from the SOUT terminal.
During receiving
The received data is stored.
When "1" is read: High level
When "0" is read: Low level
The data from the receive data buffer can be read out.
Since the sift register is provided separately from this buffer, reading can be done during a receive opera-
tion in the asynchronous mode. (The buffer function is not used in the clock synchronous mode.)
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| S1C6N3B0D0A0100 | MICROCONTROLLER, UUC54 |
| S1C6P366D0A0100 | 4-BIT, FLASH, 4.1 MHz, MICROCONTROLLER, UUC102 |
| S1C6P466D0A0A00 | MICROCONTROLLER, UUC140 |
| S1C6S2L7D | 4-BIT, MROM, 0.032 MHz, MICROCONTROLLER, UUC58 |
| S1C6S2A7F | 4-BIT, MROM, 0.08 MHz, MICROCONTROLLER, PQFP60 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| S1C-6-S | 制造商:GRIPCO 功能描述: |
| S1C7309X | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:B/W CCD PROCESSOR |
| S1C7309X01 | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:B/W CCD PROCESSOR |
| S1C88349 | 制造商:EPSON 制造商全稱:EPSON 功能描述:8-bit Single Chip Microcomputer |
| S1C88649 | 制造商:EPSON 制造商全稱:EPSON 功能描述:8-bit Single Chip Microcomputer |
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。