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參數(shù)資料
| 型號(hào)： | S1C6F567D0A0100 |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | MICROCONTROLLER, UUC141 |
| 封裝： | DIE-141 |
| 文件頁(yè)數(shù)： | 4/208頁(yè) |
| 文件大小： | 1561K |
| 代理商： | S1C6F567D0A0100 |
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S1C6F567 TECHNICAL MANUAL
EPSON
93
CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Serial Interface)
EISRC, EISTR, EISER: Interrupt mask registers (FFE3HD0, D1, D2)
Enables or disables the generation of an interrupt for the CPU.
When "1" is written: Enabled
When "0" is written: Disabled
Reading: Valid
EISRC, EISTR and EISER are interrupt mask registers that respectively correspond to the interrupt factors
for receivie completion, transmit completion and receive error. Interrupts set to "1" are enabled and
interrupts set to "0" are disabled.
At initial reset, these registers are set to "0".
ISRC, ISTR, ISER: Interrupt factor flags (FFF3HD0, D1, D2)
Indicates the serial interface interrupt generation status.
When "1" is read: Interrupt has occurred
When "0" is read: Interrupt has not occurred
When "1" is written: Flag is reset
When "0" is written: Invalid
ISRC, ISTR and ISER are interrupt factor flags that respectively correspond to the interrupts for receivie
completion, transmit completion and receive error, and are set to "1" by generation of each factor.
Transmit completion interrupt factor is generated at the point where the data transmition of the shift
register has been completed.
Receive completion interrupt factor is generated at the point where the received data has been transferred
into the receive data buffer.
Receive error interrupt factor is generated when a parity error, framing error or overrun error has been
detected during data receiving.
When set in this manner, if the corresponding interrupt enable mask is set to "1" and the CPU is set to
interrupt enabled status (I flag = "1"), an interrupt will be generated to the CPU.
Regardless of the interrupt mask register setting, the interrupt factor flag will be set to "1" by the occurrence
of an interrupt generation condition.
The interrupt factor flag is reset to "0" by writing "1".
After an interrupt occurs, the same interrupt will occur again if the interrupt enabled state (I flag = "1") is
set or the RETI instruction is executed unless the interrupt factor flag is reset. Therefore, be sure to reset
(write "1" to) the interrupt factor flag in the interrupt service routine before shifting to the interrupt
enabled state.
At initial reset, these flags are set to "0".
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