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參數(shù)資料
| 型號(hào)： | S1C6F567D0A0100 |
| 元件分類(lèi)： | 微控制器/微處理器 |
| 英文描述： | MICROCONTROLLER, UUC141 |
| 封裝： | DIE-141 |
| 文件頁(yè)數(shù)： | 190/208頁(yè) |
| 文件大?。?/td> | 1561K |
| 代理商： | S1C6F567D0A0100 |
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74
EPSON
S1C6F567 TECHNICAL MANUAL
CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Serial Interface)
4.11.2 Mask option
Since the input/output terminals of the serial interface is shared with the I/O ports (P10–P13), the
terminal specification of the I/O port is also applied to the serial interface.
In the S1C6F567, the I/O port specification is fixed at "with pull-up resistor" and "complementary
output".
Therefore, the output specification of the terminals SOUT, SCLK (in master mode) and SRDY (in slave
mode) that are used as output in the input/output port of the serial interface is fixed at complementary
output.
Furthermore, a pull-up resistor is provided for the SIN terminal and the SCLK terminal (for clock syn-
chronous slave mode) that are used as input terminals.
4.11.3 Transfer modes
There are four transfer modes for the serial interface and mode selection is made by setting the two bits of
the mode selection registers SMD0 and SMD1 as shown in the table below.
Table 4.11.3.1 Transfer modes
SMD1
SMD0
Mode
1
0
1
0
1
0
8-bit asynchronous
7-bit asynchronous
Clock synchronous slave
Clock synchronous master
Table 4.11.3.2 Terminal settings corresponding to each transfer mode
Mode
SIN
Asynchronous 8-bit
Asynchronous 7-bit
Clock synchronous slave
Clock synchronous master
P13
Output
P13
SOUT SCLK
SRDY
P12
Input
Output
Input
At initial reset, transfer mode is set to clock synchronous master mode.
Clock synchronous master mode
In this mode, the internal clock is utilized as a synchronous clock for the built-in shift registers, and 8-
bit clock synchronous serial transfers can be performed with this serial interface as the master.
The synchronous clock is also output from the SCLK terminal which enables control of the external
(slave side) serial I/O device. Since the SRDY terminal is not utilized in this mode, it can be used as an
I/O port.
Figure 4.11.3.1(a) shows the connection example of input/output terminals in the clock synchronous
master mode.
Clock synchronous slave mode
In this mode, a synchronous clock from the external (master side) serial input/output device is
utilized and 8-bit clock synchronous serial transfers can be performed with this serial interface as the
slave.
The synchronous clock is input to the SCLK terminal and is utilized by this interface as the synchro-
nous clock.
Furthermore, the SRDY signal indicating the transmit-receive ready status is output from the SRDY
terminal in accordance with the serial interface operating status.
In the slave mode, the settings for registers SCS0 and SCS1 used to select the clock source are invalid.
Figure 4.11.3.1(b) shows the connection example of input/output terminals in the clock synchronous
slave mode.
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