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參數(shù)資料
| 型號(hào)： | S1C6F567D0A0100 |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | MICROCONTROLLER, UUC141 |
| 封裝： | DIE-141 |
| 文件頁(yè)數(shù)： | 189/208頁(yè) |
| 文件大小： | 1561K |
| 代理商： | S1C6F567D0A0100 |
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S1C6F567 TECHNICAL MANUAL
EPSON
73
CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Serial Interface)
4.11 Serial Interface
4.11.1 Configuration of serial interface
The S1C6F567 incorporates a full duplex serial interface (when asynchronous system is selected) that
allows the user to select either clock synchronous system or asynchronous system.
The data transfer method can be selected in software.
When the clock synchronous system is selected, 8-bit data transfer is possible.
When the asynchronous system is selected, either 7-bit or 8-bit data transfer is possible, and a parity
check of received data and the addition of a parity bit for transmitting data can automatically be done by
selecting in software.
Figure 4.11.1.1 shows the configuration of the serial interface.
fOSC3
Data bus
SOUT(P11)
Serial I/O control
& status register
Received
data buffer
Interrupt
control circuit
Serial input
control circuit
Received data
shift register
Transmitting data
shift register
Serial output
control circuit
SIN(P10)
Clock
control circuit
READY output
control circuit
SCLK(P12)
Error detection
circuit
SRDY(P13)
Start bit
detection circuit
Programmable timer 1 underflow signal
Interrupt
request
OSC3 oscillation circuit
Fig. 4.11.1.1 Configuration of serial interface
Serial interface input/output terminals, SIN, SOUT, SCLK and SRDY are shared with the I/O ports P10–
P13. In order to utilize these terminals for the serial interface input/output terminals, proper settings have
to be made with registers ESIF, SMD0 and SMD1. (At initial reset, these terminals are set as I/O port
terminals.)
The direction of I/O port terminals set for serial interface input/output terminals are determined by the
signal and transfer mode for each terminal. Furthermore, the settings for the corresponding I/O control
registers for the I/O ports become invalid.
Table 4.11.1.1 Configuration of input/output terminals
Terminal
When serial interface is selected
P10
P11
P12
P13
SIN
SOUT
SCLK
SRDY
* The terminals used may vary depending on the transfer mode.
SIN and SOUT are serial data input and output terminals which function identically in clock synchronous
system and asynchronous system. SCLK is exclusively for use with clock synchronous system and func-
tions as a synchronous clock input/output terminal. SRDY is exclusively for use in clock synchronous
slave mode and functions as a send-receive ready signal output terminal.
When asynchronous system is selected, since SCLK and SRDY are superfluous, the I/O port terminals P12
and P13 can be used as I/O ports.
In the same way, when clock synchronous master mode is selected, since SRDY is superfluous, the I/O port
terminal P13 can be used as I/O port.
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