- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄98068 > S1C6F567D0A0100 MICROCONTROLLER, UUC141 PDF資料下載
參數(shù)資料
| 型號： | S1C6F567D0A0100 |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | MICROCONTROLLER, UUC141 |
| 封裝： | DIE-141 |
| 文件頁數(shù)： | 201/208頁 |
| 文件大?。?/td> | 1561K |
| 代理商： | S1C6F567D0A0100 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁第77頁第78頁第79頁第80頁第81頁第82頁第83頁第84頁第85頁第86頁第87頁第88頁第89頁第90頁第91頁第92頁第93頁第94頁第95頁第96頁第97頁第98頁第99頁第100頁第101頁第102頁第103頁第104頁第105頁第106頁第107頁第108頁第109頁第110頁第111頁第112頁第113頁第114頁第115頁第116頁第117頁第118頁第119頁第120頁第121頁第122頁第123頁第124頁第125頁第126頁第127頁第128頁第129頁第130頁第131頁第132頁第133頁第134頁第135頁第136頁第137頁第138頁第139頁第140頁第141頁第142頁第143頁第144頁第145頁第146頁第147頁第148頁第149頁第150頁第151頁第152頁第153頁第154頁第155頁第156頁第157頁第158頁第159頁第160頁第161頁第162頁第163頁第164頁第165頁第166頁第167頁第168頁第169頁第170頁第171頁第172頁第173頁第174頁第175頁第176頁第177頁第178頁第179頁第180頁第181頁第182頁第183頁第184頁第185頁第186頁第187頁第188頁第189頁第190頁第191頁第192頁第193頁第194頁第195頁第196頁第197頁第198頁第199頁第200頁當前第201頁第202頁第203頁第204頁第205頁第206頁第207頁第208頁
84
EPSON
S1C6F567 TECHNICAL MANUAL
CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Serial Interface)
Data receive procedure
The control procedure and operation during receiving is as follows.
(1) Write "0" in the receive enable register
RXEN to set the receiving disable status
and to reset the respective PER, OER,
FER flags that indicate parity, overrun
and framing errors.
(2) Write "1" in the receive enable register
RXEN to set into the receiving enable
status.
(3) The shift clock will change to enable
from the point where the start bit
(LOW) has been input from the SIN
terminal and the receive data will be
synchronized to the rising edge follow-
ing the second clock, and will thus be
successively incorporated into the shift
register.
After data bits have been incorporated,
the stop bit is checked and, if it is not
HIGH, it becomes a framing error and the
error interrupt factor flag ISER is set to
"1". When interrupt has been enabled, an
error interrupt is generated at this point.
When receiving is completed, data in
the shift register is transferred to the
receive data buffer and the receiving
complete interrupt flag ISRC is set to
"1". When interrupt has been enabled, a
receiving complete interrupt is gener-
ated at this point. (When an overrun
error is generated, the interrupt factor
flag ISRC is not set to "1" and a receiv-
ing complete interrupt is not gener-
ated.)
End
RXEN
← 1
No
Yes
Receiving interrupt ?
Yes
Receiving complete ?
Received data reading
from TRXD0–TRXD7
RXEN
← 0
RXTRG
← 1
No
Yes
Error generated ?
Error processing
Data receiving
RXEN
← 0
Resets error flags
PER, OER and FER
No
If "with parity check" has been selected, a parity check is executed when data is transferred into the
receive data buffer from the shift register and if a parity error is detected, the error interrupt factor
flag is set to "1". When the interrupt has been enabled, an error interrupt is generated at this point just
as in the framing error mentioned above.
(4) Read the received data from TRXD0–TRXD7 using receiving complete interrupt.
(5) Write "1" to the receive control bit RXTRG to inform that the receive data has been read out.
When the following data is received prior to writing "1" to RXTRG, it is recognized as an overrun
error and the error interrupt factor flag is set to "1". When the interrupt has been enabled, an error
interrupt is generated at this point just as in the framing error and parity error mentioned above.
(6) Repeat steps (3) to (5) for the number of bytes of receiving data, and then set the receive disable status
by writing "0" to the receive enable register RXEN, when the receiving is completed.
Fig. 4.11.7.3 Receiving procedure in asynchronous mode
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| S1C6N3B0D0A0100 | MICROCONTROLLER, UUC54 |
| S1C6P366D0A0100 | 4-BIT, FLASH, 4.1 MHz, MICROCONTROLLER, UUC102 |
| S1C6P466D0A0A00 | MICROCONTROLLER, UUC140 |
| S1C6S2L7D | 4-BIT, MROM, 0.032 MHz, MICROCONTROLLER, UUC58 |
| S1C6S2A7F | 4-BIT, MROM, 0.08 MHz, MICROCONTROLLER, PQFP60 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| S1C-6-S | 制造商:GRIPCO 功能描述: |
| S1C7309X | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:B/W CCD PROCESSOR |
| S1C7309X01 | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:B/W CCD PROCESSOR |
| S1C88349 | 制造商:EPSON 制造商全稱:EPSON 功能描述:8-bit Single Chip Microcomputer |
| S1C88649 | 制造商:EPSON 制造商全稱:EPSON 功能描述:8-bit Single Chip Microcomputer |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。