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| 型號(hào)： | S1C6F567D0A0100 |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | MICROCONTROLLER, UUC141 |
| 封裝： | DIE-141 |
| 文件頁(yè)數(shù)： | 156/208頁(yè) |
| 文件大小： | 1561K |
| 代理商： | S1C6F567D0A0100 |
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S1C6F567 TECHNICAL MANUAL
EPSON
43
CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (I/O Ports)
Table 4.6.6.1(b) Control bits of I/O ports
Address
Comment
D3
D2
Register
D1
D0
Name
Init 1
10
FF4CH
IOC33
IOC32
IOC31
IOC30
R/W
IOC33
IOC32
IOC31
IOC30
0
Output
Input
P30–P33 I/O control register
FF4DH
PUL33
PUL32
PUL31
PUL30
R/W
PUL33
PUL32
PUL31
PUL30
1
On
Off
P30–P33 pull-up control register
FF4EH
P33
P32
P31
P30
R/W
P33
P32
P31
P30
– 2
High
Low
P30–P33 I/O port data
FF61H
EXLCDC ALOFF
ALON
LPAGE
R/W
EXLCDC
ALOFF
ALON
LPAGE
0
1
0
Enable
All Off
All On
F100-F14F
Disable
Normal
F000-F04F
Expanded LCD driver signal control
LCD all Off control
LCD all On control
Display memory area selection (when 1/8 duty is selected)
General-purpose register when 1/16, 1/17 duty is selected
0
Clk-sync. master
2
Async. 7-bit
1
Clk-sync. slave
3
Async. 8-bit
[SMD1, 0]
Mode
[SMD1, 0]
Mode
FF70H
0
SMD1
SMD0
ESIF
RR/W
0 3
SMD1
SMD0
ESIF
– 2
0
SIF
I/O
Unused
Serial I/F
mode selection
Serial I/F enable (P1x port function selection)
*1 Initial value at initial reset
*2 Not set in the circuit
*3 Constantly "0" when being read
(1) Selection of port function
EXLCDC: Expanded LCD driver signal control register (FF61HD3)
Sets P22 and P23 to the CL signal and the FR signal output ports.
When "1" is written: CL/FR signal output
When "0" is written: I/O port
Reading: Valid
When setting P22 to the CL (LCD synchronous signal) output and P23 to the FR (LCD frame signal)
output, write "1" to this register and when they are used as I/O ports, write "0".
The CL and FR signals are output from the P22 terminal and P23 terminal immediately after the functions
are switched by the EXLCDC register. In this case, the control registers for P22 and P23 can be used as
general purpose registers that do not affect the output.
At initial reset, this register is set to "0".
ESIF: Serial interface enable register (FF70HD0)
Selects function for P10–P13.
When "1" is written: Serial interface input/output port
When "0" is written: I/O port
Reading: Valid
When using the serial interface, write "1" to this register and when P10–P13 are used as the I/O port,
write "0". The terminal configuration within P10–P13 that are used for the serial interface is decided by
the transfer mode (7-bit asynchronous, 8-bit asynchronous, clock synclonous slave, clock synchronous
master) selected with the SMD1 and SMD0 registers.
In the clock synchronous slave mode, all the P10–P13 ports are set to the serial interface input/output
port. In the clock synchronous master mode, P10–P12 are set to the serial interface input/output port and
P13 can be used as the I/O port. In the 8/7-bit asynchronous mode, P10 and P11 are set to the serial
interface input/output port and P12 and P13 can be used as the I/O port.
At initial reset, this register is set to "0".
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