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參數(shù)資料
| 型號(hào)： | S1C63406F |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 4-BIT, MROM, 4.2 MHz, MICROCONTROLLER, PQFP128 |
| 封裝： | PLASTIC, TQFP15-128 |
| 文件頁(yè)數(shù)： | 61/144頁(yè) |
| 文件大?。?/td> | 1160K |
| 代理商： | S1C63406F |
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S1C63406 TECHNICAL MANUAL
EPSON
15
CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Memory Map)
Table 4.1.1 (a) I/O memory map (FF00H–FF4AH)
Remarks
1 Initial value at initial reset 2 Not set in the circuit 3 Constantly "0" when being read
Address
Comment
D3
D2
Register
D1
D0
Name
Init 1
10
FF06H
FOUTE FOFQ2 FOFQ1 FOFQ0
R/W
FOUTE
FOFQ2
FOFQ1
FOFQ0
0
Enable
Disable FOUT enable
FOUT
frequency
selection
FF07H
HLMOD
0
WDEN WDRST
R/W
R
R/W
W
HLMOD
0 3
WDEN
WDRST3
0
– 2
1
Reset
On
Enable
Reset
Off
Disable
Invalid
Heavy load protection
Unused
Watchdog timer enable
Watchdog timer reset (writing)
FF00H
CLKCHG OSCC
VDC1
VDC0
R/W
CLKCHG
OSCC
VDC1
VDC0
0
OSC3
On
OSC1
Off
CPU clock switch
OSC3 oscillation On/Off
CPU operating
voltage switch
FF42H
K03
K02
K01
K00
R
K03
K02
K01
K00
– 2
High
Low
K00–K03 input port data
FF43H
00
K0NR1
K0NR0
R
R/W
0 3
K0NR1
K0NR0
– 2
0
Unused
K0 interrupt
noise rejector
0
fOSC1/64
4
fOSC1/4
1
fOSC1/32
5
fOSC1
2
fOSC1/16
6
fOSC3/2
3
fOSC1/8
7
fOSC3
[FOFQ2–0]
Frequency
[FOFQ2–0]
Frequency
0
1.1
1
1.3
2
1.5
3
1.7
[VDC1, 0]
VD1 (V)
0
Off
1
0.5ms
2
2.0ms
3
7.8ms
[K0NR1, 0]
NR
FF46H
R13
R12
R11
R10
R/W
R13
R12
R11
R10
1
High
Low
R13 output port data (FOUTE=0)
Fix at "1" when FOUT is used (FOUTE=1)
R12 output port data (PTOUT=0)
Fix at "1" when TOUT is used (PTOUT=1)
R11 output port data
R10 output port data
FF05H
00
SVDDT SVDON
R
R/W
0 3
SVDDT
SVDON
– 2
0
Low
On
Normal
Off
Unused
SVD evaluation data
SVD circuit On/Off
FF04H
SVDS3 SVDS2 SVDS1 SVDS0
R/W
SVDS3
SVDS2
SVDS1
SVDS0
0
SVD criteria voltage setting
0
1.30
8
2.10
1
1.40
9
2.20
2
1.50
10
2.30
3
1.60
11
2.40
4
1.70
12
2.50
5
1.80
13
2.60
6
1.90
14
2.70
7
2.00
15
2.80
[SVDS3–0]
Voltage(V)
[SVDS3–0]
Voltage(V)
FF49H
PPL23
PPL22
PPL21
PPL20
R/W
PPL23
PPL22
PPL21
PPL20
1
On
Off
P23 pull-up control register
General-purpose register when SIF (clock sync. slave) is selected
P22 pull-up control register
General-purpose register when SIF (clock sync. master) is selected
SCLK (I) pull-up control register
when SIF (clock sync. slave) is selected
P21 pull-up control register (ESIF=0)
General-purpose register when SIF is selected
P20 pull-up control register (ESIF=0)
SIN pull-up control register when SIF is selected
FF4AH
P23
(XSRDY)
P22
(XSCLK)
P21
(SOUT)
P20
(SIN)
R/W
P23
P22
P21
P20
– 2
High
Low
P23 I/O port data
General-purpose register when SIF (clock sync. slave) is selected
P22 I/O port data
General-purpose register when SIF (clock sync.) is selected
P21 I/O port data (ESIF=0)
General-purpose register when SIF is selected
P20 I/O port data (ESIF=0)
General-purpose register when SIF is selected
FF48H
IOC23
IOC22
IOC21
IOC20
R/W
IOC23
IOC22
IOC21
IOC20
0
Output
Input
P23 I/O control register
General-purpose register when SIF (clock sync. slave) is selected
P22 I/O control register
General-purpose register when SIF (clock sync.) is selected
P21 I/O control register (ESIF=0)
General-purpose register when SIF is selected
P20 I/O control register (ESIF=0)
General-purpose register when SIF is selected
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