參數(shù)資料
型號(hào): S1C63406F
元件分類: 微控制器/微處理器
英文描述: 4-BIT, MROM, 4.2 MHz, MICROCONTROLLER, PQFP128
封裝: PLASTIC, TQFP15-128
文件頁(yè)數(shù): 18/144頁(yè)
文件大小: 1160K
代理商: S1C63406F
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106
EPSON
S1C63406 TECHNICAL MANUAL
CHAPTER 5: SUMMARY OF NOTES
(2) Be sure to turn the noise rejector OFF before executing the SLP instruction.
(3) Reactivating from SLEEP status can only be done by generation of an input interrupt factor. Therefore
when using the SLEEP function, it is necessary to set the interrupt selection register (SIK0x = "1") of
the port to be used for releasing SLEEP status before executing the SLP instruction. Furthermore,
enable the input port interrupt using the corresponding interrupt mask register (EIK0x = "1") before
executing the SLP instruction to run input interrupt handler routine after SLEEP status is released.
(4) Each input port (K00–K03) has a different interrupt factor, thus the input interrupt is controlled
individually. Be aware that this interrupt configuration is different from that of the previous models.
(5) The K03 terminal functions as the clock input terminal for the programmable timer, and the input
signal is shared with the input port and the programmable timer. Therefore, when the K03 terminal is
set to the clock input terminal for the programmable timer, take care of the interrupt setting.
Output port
(1) When using the output port (R12, R13) as the special output port, fix the data register (R12, R13) at
"1". Be aware that the output terminal is fixed at a low (VSS) level the same as the DC output if "0" is
written to the R12 and R13 registers when the special output has been selected.
(2) A hazard may occur when the FOUT signal and the TOUT signal are turned ON and OFF.
(3) When fOSC3 is selected for the FOUT signal frequency, it is necessary to control the OSC3 oscillation
circuit before output. Refer to Section 4.3, "Oscillation Circuit", for the control and notes.
I/O port
When I/O ports are changed from low to high by pull-up resistor in the input mode, the rise of the
waveform is delayed on account of the time constant of the pull-up resistor and input gate capaci-
tance. Hence, when fetching input ports, set an appropriate wait time.
Particular care needs to be taken of the key scan during key matrix configuration.
Make this waiting time the amount of time or more calculated by the following expression.
10
× C × R
C: terminal capacitance 5 pF + parasitic capacitance ? pF
R: pull-up resistance 300 k
LCD driver
(1) Current consumption will be increased for a cycle of 1 kHz to stabilize the LCD power quickly after
setting LPWR on.
(2) When a program that access no memory mounted area (F078H–F0FFH, F101H, F103H, , F177H) is
made, the operation is not guaranteed.
(3) Because at initial reset, the contents of display memory and LC3–LC0 (LCD contrast) are undefined,
there is need to initialize by the software. Furthermore, take care of the registers LPWR and ALOFF
because these are set so that the display goes OFF.
Clock timer
(1) Be sure to read timer data in the order of low-order data (TM0–TM3) then high-order data (TM4–TM7).
(2) When the CR oscillation circuit is selected as the OSC1 oscillation circuit by mask option, the frequen-
cies and times differ from the values described in this section because the oscillation frequency will be
60 kHz (Typ.). Therefore, the clock timer can not be used for the clock function.
Stopwatch timer
(1) When data of the counter is read at run mode, perform the reading after suspending the counter once
and then set SWRUN to "1" again. Moreover, it is required that the suspension period not exceed 976
sec (1/4 cycle of 256 Hz).
(2) When the CR oscillation circuit is selected as the OSC1 oscillation circuit by mask option, the frequen-
cies and times differ from the values described in this section because the oscillation frequency will be
60 kHz (Typ.). Therefore, this timer can not be used for the stopwatch function.
Programmable timer
(1) When reading counter data, be sure to read the low-order 4 bits (PTD00–PTD03, PTD10–PTD13) first.
Furthermore, the high-order 4 bits (PTD04–PTD07, PTD14–PTD17) should be read within 0.73 msec
(when fOSC1 is 32.768 kHz) of reading the low-order 4 bits (PTD00–PTD03, PTD10–PTD13).
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