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參數資料
| 型號： | S1C60L16F0A0100 |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 4-BIT, MROM, 0.032768 MHz, MICROCONTROLLER, PQFP80 |
| 封裝： | PLASTIC, QFP14-80 |
| 文件頁數： | 86/105頁 |
| 文件大小： | 841K |
| 代理商： | S1C60L16F0A0100 |
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S1C60N16 TECHNICAL MANUAL
EPSON
71
CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Interrupt and HALT)
4.16.1 Interrupt factors
Table 4.16.1.1 shows the factors for generating interrupt requests.
The interrupt flags are set to "1" depending on the corresponding interrupt factors.
The CPU operation is interrupted when any of the conditions below set an interrupt factor flag to "1".
The corresponding mask register is "1" (enabled)
The interrupt flag is "1" (EI)
The interrupt factor flag is a read-only register, but can be reset to "0" when the register data is read out.
At initial reset, the interrupt factor flags are reset to "0".
Note: Read the interrupt factor flags only in the DI status (interrupt flag = "0"). A malfunction could result
from read-out during the EI status (interrupt flag = "1").
Table 4.16.1.1 Interrupt factors
Interrupt factor
Clock timer 2 Hz falling edge
Clock timer 8 Hz falling edge
Clock timer 32 Hz falling edge
Stopwatch timer 1 Hz falling edge
Stopwatch timer 10 Hz falling edge
Serial interface
When 8-bit data input/output has completed
Input (K00–K03) port rising/falling edge
Input (K10) port rising/falling edge
Interrupt factor flag
TI2
(2E9HD2)
TI8
(2E9HD1)
TI32
(2E9HD0)
SWIT1 (2EAHD1)
SWIT0 (2EAHD0)
ISIO
(2F3HD0)
IK0
(2EAHD2)
IK1
(2EAHD3)
4.16.2 Specific masks and factor flags for interrupt
The interrupt factor flags can be masked by the corresponding interrupt mask registers.
The interrupt mask registers are read/write registers. They are enabled (interrupt authorized) when "1" is
written to them, and masked (interrupt inhibited) when "0" is written to them.
At initial reset, the interrupt mask register is set to "0".
Table 4.16.2.1 shows the correspondence between interrupt mask registers and interrupt factor flags.
Table 4.16.2.1 Interrupt mask registers and interrupt factor flags
Interrupt mask register
ETI2
(2E8HD2)
ETI8
(2E8HD1)
ETI32
(2E8HD0)
EISWIT1 (2E6HD1)
EISWIT0 (2E6HD0)
EISIO
(2F2HD0)
EIK03*
(2E5HD3)
EIK02*
(2E5HD2)
EIK01*
(2E5HD1)
EIK00*
(2E5HD0)
EIK10*
(2E7HD2)
Interrupt factor flag
TI2
(2E9HD2)
TI8
(2E9HD1)
TI32
(2E9HD0)
SWIT1 (2EAHD1)
SWIT0 (2EAHD0)
ISIO
(2F3HD0)
IK0
(2EAHD2)
IK1
(2EAHD3)
There is an interrupt mask register for each pin of the input ports.
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